Macro name | Arguments | Value |
_RAMSIZE | none | 2048 |
__18F4550 | none | 1 |
__18F4550__ | none | 1 |
_HTC_VER_PATCH_ | none | 48 |
_FLASH_ERASE_SIZE | none | 64 |
_PLIB | none | 1 |
__PICC18__ | none | 1 |
_HTC_VER_MAJOR_ | none | 10 |
_ROMSIZE | none | 32768 |
__CCI__ | none | 1 |
_HTC_VER_PLVL_ | none | 0 |
_HTC_EDITION_ | none | 0 |
__XC8 | none | 1 |
__XC8__ | none | 1 |
__STACK_REENTRANT | none | 4 |
_HTC_VER_MINOR_ | none | 21 |
__XC | none | 1 |
__XC__ | none | 1 |
_ERRATA_TYPES | none | 2 |
__DATE__ | none | "Feb 16 2015" |
_FLASH_WRITE_SIZE | none | 32 |
__STACK_HYBRID | none | 2 |
__XC8_VERSION | none | 1210 |
_MPC_ | none | 1 |
__FILE__ | none | dynamic replacement |
_18F4550 | none | 1 |
_PIC18 | none | 1 |
__LINE__ | none | dynamic replacement |
_18F4550_FAMILY_ | none | 1 |
_EEPROMSIZE | none | 256 |
__STACK_COMPILED | none | 1 |
__TRADITIONAL18__ | none | 1 |
__STDC__ | none | 1 |
__TIME__ | none | "22:05:39" |
_OMNI_CODE_ | none | 1 |
__STACK | none | __STACK_COMPILED |
_CCI_H_ | none | |
___AT_H_ | none | |
__at | 1 | __attribute__((address(<0>))) |
__deprecate | none | __attribute__((deprecated)) |
__cp0 | 1 | __attribute__((unsupported("the __cp0() construct is not supported by this architecture"))) |
__cp0 | empty | __attribute__((unsupported("the __cp0() construct is not supported by this architecture"))) |
__abi | 1 | __attribute__((unsupported("the __abi() construct is not supported by this architecture"))) |
__abi | empty | __attribute__((unsupported("the __abi() construct is not supported by this architecture"))) |
__align | empty | __attribute__((unsupported("the __align() attribute is not used by this compiler"))) |
__align | 1 | __attribute__((unsupported("the __align() attribute is not used by this compiler"))) |
__xdata | none | __attribute__((unsupported("__xdata is not defined on this architecture"))) |
__ydata | none | __attribute__((unsupported("__ydata in not defined on this architecture"))) |
__interrupt | 1 | __attribute__((interrupt(___mkstr(__<0>)))) |
PIC18F4550_CONFIG_H | none | |
_XC_H_ | none | |
_HTC_H_ | none | |
__LITE__ | none | 0 |
__STD__ | none | 1 |
__PRO__ | none | 2 |
___mkstr1 | 1 | <0> |
___mkstr | 1 | ___mkstr1(<0>) |
_OMNITARGET | none | ((void *)0xFFFFFFFF) |
_PIC18_H | none | |
_PIC18_CHIP_SELECT_H_ | none | |
_HEADER_NOT_FOUND | none | |
_PIC18F4550_H_ | none | |
_SPPDATA_DATA_POSN | none | 0x0 |
_SPPDATA_DATA_POSITION | none | 0x0 |
_SPPDATA_DATA_SIZE | none | 0x8 |
_SPPDATA_DATA_LENGTH | none | 0x8 |
_SPPDATA_DATA_MASK | none | 0xFF |
_SPPCFG_WS_POSN | none | 0x0 |
_SPPCFG_WS_POSITION | none | 0x0 |
_SPPCFG_WS_SIZE | none | 0x4 |
_SPPCFG_WS_LENGTH | none | 0x4 |
_SPPCFG_WS_MASK | none | 0xF |
_SPPCFG_CLK1EN_POSN | none | 0x4 |
_SPPCFG_CLK1EN_POSITION | none | 0x4 |
_SPPCFG_CLK1EN_SIZE | none | 0x1 |
_SPPCFG_CLK1EN_LENGTH | none | 0x1 |
_SPPCFG_CLK1EN_MASK | none | 0x10 |
_SPPCFG_CSEN_POSN | none | 0x5 |
_SPPCFG_CSEN_POSITION | none | 0x5 |
_SPPCFG_CSEN_SIZE | none | 0x1 |
_SPPCFG_CSEN_LENGTH | none | 0x1 |
_SPPCFG_CSEN_MASK | none | 0x20 |
_SPPCFG_CLKCFG_POSN | none | 0x6 |
_SPPCFG_CLKCFG_POSITION | none | 0x6 |
_SPPCFG_CLKCFG_SIZE | none | 0x2 |
_SPPCFG_CLKCFG_LENGTH | none | 0x2 |
_SPPCFG_CLKCFG_MASK | none | 0xC0 |
_SPPCFG_WS0_POSN | none | 0x0 |
_SPPCFG_WS0_POSITION | none | 0x0 |
_SPPCFG_WS0_SIZE | none | 0x1 |
_SPPCFG_WS0_LENGTH | none | 0x1 |
_SPPCFG_WS0_MASK | none | 0x1 |
_SPPCFG_WS1_POSN | none | 0x1 |
_SPPCFG_WS1_POSITION | none | 0x1 |
_SPPCFG_WS1_SIZE | none | 0x1 |
_SPPCFG_WS1_LENGTH | none | 0x1 |
_SPPCFG_WS1_MASK | none | 0x2 |
_SPPCFG_WS2_POSN | none | 0x2 |
_SPPCFG_WS2_POSITION | none | 0x2 |
_SPPCFG_WS2_SIZE | none | 0x1 |
_SPPCFG_WS2_LENGTH | none | 0x1 |
_SPPCFG_WS2_MASK | none | 0x4 |
_SPPCFG_WS3_POSN | none | 0x3 |
_SPPCFG_WS3_POSITION | none | 0x3 |
_SPPCFG_WS3_SIZE | none | 0x1 |
_SPPCFG_WS3_LENGTH | none | 0x1 |
_SPPCFG_WS3_MASK | none | 0x8 |
_SPPCFG_CLKCFG0_POSN | none | 0x6 |
_SPPCFG_CLKCFG0_POSITION | none | 0x6 |
_SPPCFG_CLKCFG0_SIZE | none | 0x1 |
_SPPCFG_CLKCFG0_LENGTH | none | 0x1 |
_SPPCFG_CLKCFG0_MASK | none | 0x40 |
_SPPCFG_CLKCFG1_POSN | none | 0x7 |
_SPPCFG_CLKCFG1_POSITION | none | 0x7 |
_SPPCFG_CLKCFG1_SIZE | none | 0x1 |
_SPPCFG_CLKCFG1_LENGTH | none | 0x1 |
_SPPCFG_CLKCFG1_MASK | none | 0x80 |
_SPPEPS_ADDR_POSN | none | 0x0 |
_SPPEPS_ADDR_POSITION | none | 0x0 |
_SPPEPS_ADDR_SIZE | none | 0x4 |
_SPPEPS_ADDR_LENGTH | none | 0x4 |
_SPPEPS_ADDR_MASK | none | 0xF |
_SPPEPS_SPPBUSY_POSN | none | 0x4 |
_SPPEPS_SPPBUSY_POSITION | none | 0x4 |
_SPPEPS_SPPBUSY_SIZE | none | 0x1 |
_SPPEPS_SPPBUSY_LENGTH | none | 0x1 |
_SPPEPS_SPPBUSY_MASK | none | 0x10 |
_SPPEPS_WRSPP_POSN | none | 0x6 |
_SPPEPS_WRSPP_POSITION | none | 0x6 |
_SPPEPS_WRSPP_SIZE | none | 0x1 |
_SPPEPS_WRSPP_LENGTH | none | 0x1 |
_SPPEPS_WRSPP_MASK | none | 0x40 |
_SPPEPS_RDSPP_POSN | none | 0x7 |
_SPPEPS_RDSPP_POSITION | none | 0x7 |
_SPPEPS_RDSPP_SIZE | none | 0x1 |
_SPPEPS_RDSPP_LENGTH | none | 0x1 |
_SPPEPS_RDSPP_MASK | none | 0x80 |
_SPPEPS_ADDR0_POSN | none | 0x0 |
_SPPEPS_ADDR0_POSITION | none | 0x0 |
_SPPEPS_ADDR0_SIZE | none | 0x1 |
_SPPEPS_ADDR0_LENGTH | none | 0x1 |
_SPPEPS_ADDR0_MASK | none | 0x1 |
_SPPEPS_ADDR1_POSN | none | 0x1 |
_SPPEPS_ADDR1_POSITION | none | 0x1 |
_SPPEPS_ADDR1_SIZE | none | 0x1 |
_SPPEPS_ADDR1_LENGTH | none | 0x1 |
_SPPEPS_ADDR1_MASK | none | 0x2 |
_SPPEPS_ADDR2_POSN | none | 0x2 |
_SPPEPS_ADDR2_POSITION | none | 0x2 |
_SPPEPS_ADDR2_SIZE | none | 0x1 |
_SPPEPS_ADDR2_LENGTH | none | 0x1 |
_SPPEPS_ADDR2_MASK | none | 0x4 |
_SPPEPS_ADDR3_POSN | none | 0x3 |
_SPPEPS_ADDR3_POSITION | none | 0x3 |
_SPPEPS_ADDR3_SIZE | none | 0x1 |
_SPPEPS_ADDR3_LENGTH | none | 0x1 |
_SPPEPS_ADDR3_MASK | none | 0x8 |
_SPPEPS_BUSY_POSN | none | 0x4 |
_SPPEPS_BUSY_POSITION | none | 0x4 |
_SPPEPS_BUSY_SIZE | none | 0x1 |
_SPPEPS_BUSY_LENGTH | none | 0x1 |
_SPPEPS_BUSY_MASK | none | 0x10 |
_SPPCON_SPPEN_POSN | none | 0x0 |
_SPPCON_SPPEN_POSITION | none | 0x0 |
_SPPCON_SPPEN_SIZE | none | 0x1 |
_SPPCON_SPPEN_LENGTH | none | 0x1 |
_SPPCON_SPPEN_MASK | none | 0x1 |
_SPPCON_SPPOWN_POSN | none | 0x1 |
_SPPCON_SPPOWN_POSITION | none | 0x1 |
_SPPCON_SPPOWN_SIZE | none | 0x1 |
_SPPCON_SPPOWN_LENGTH | none | 0x1 |
_SPPCON_SPPOWN_MASK | none | 0x2 |
_UFRML_FRM_POSN | none | 0x0 |
_UFRML_FRM_POSITION | none | 0x0 |
_UFRML_FRM_SIZE | none | 0x8 |
_UFRML_FRM_LENGTH | none | 0x8 |
_UFRML_FRM_MASK | none | 0xFF |
_UFRML_FRM0_POSN | none | 0x0 |
_UFRML_FRM0_POSITION | none | 0x0 |
_UFRML_FRM0_SIZE | none | 0x1 |
_UFRML_FRM0_LENGTH | none | 0x1 |
_UFRML_FRM0_MASK | none | 0x1 |
_UFRML_FRM1_POSN | none | 0x1 |
_UFRML_FRM1_POSITION | none | 0x1 |
_UFRML_FRM1_SIZE | none | 0x1 |
_UFRML_FRM1_LENGTH | none | 0x1 |
_UFRML_FRM1_MASK | none | 0x2 |
_UFRML_FRM2_POSN | none | 0x2 |
_UFRML_FRM2_POSITION | none | 0x2 |
_UFRML_FRM2_SIZE | none | 0x1 |
_UFRML_FRM2_LENGTH | none | 0x1 |
_UFRML_FRM2_MASK | none | 0x4 |
_UFRML_FRM3_POSN | none | 0x3 |
_UFRML_FRM3_POSITION | none | 0x3 |
_UFRML_FRM3_SIZE | none | 0x1 |
_UFRML_FRM3_LENGTH | none | 0x1 |
_UFRML_FRM3_MASK | none | 0x8 |
_UFRML_FRM4_POSN | none | 0x4 |
_UFRML_FRM4_POSITION | none | 0x4 |
_UFRML_FRM4_SIZE | none | 0x1 |
_UFRML_FRM4_LENGTH | none | 0x1 |
_UFRML_FRM4_MASK | none | 0x10 |
_UFRML_FRM5_POSN | none | 0x5 |
_UFRML_FRM5_POSITION | none | 0x5 |
_UFRML_FRM5_SIZE | none | 0x1 |
_UFRML_FRM5_LENGTH | none | 0x1 |
_UFRML_FRM5_MASK | none | 0x20 |
_UFRML_FRM6_POSN | none | 0x6 |
_UFRML_FRM6_POSITION | none | 0x6 |
_UFRML_FRM6_SIZE | none | 0x1 |
_UFRML_FRM6_LENGTH | none | 0x1 |
_UFRML_FRM6_MASK | none | 0x40 |
_UFRML_FRM7_POSN | none | 0x7 |
_UFRML_FRM7_POSITION | none | 0x7 |
_UFRML_FRM7_SIZE | none | 0x1 |
_UFRML_FRM7_LENGTH | none | 0x1 |
_UFRML_FRM7_MASK | none | 0x80 |
_UFRML_FRML_POSN | none | 0x0 |
_UFRML_FRML_POSITION | none | 0x0 |
_UFRML_FRML_SIZE | none | 0x8 |
_UFRML_FRML_LENGTH | none | 0x8 |
_UFRML_FRML_MASK | none | 0xFF |
_UFRMH_FRM_POSN | none | 0x0 |
_UFRMH_FRM_POSITION | none | 0x0 |
_UFRMH_FRM_SIZE | none | 0x3 |
_UFRMH_FRM_LENGTH | none | 0x3 |
_UFRMH_FRM_MASK | none | 0x7 |
_UFRMH_FRM8_POSN | none | 0x0 |
_UFRMH_FRM8_POSITION | none | 0x0 |
_UFRMH_FRM8_SIZE | none | 0x1 |
_UFRMH_FRM8_LENGTH | none | 0x1 |
_UFRMH_FRM8_MASK | none | 0x1 |
_UFRMH_FRM9_POSN | none | 0x1 |
_UFRMH_FRM9_POSITION | none | 0x1 |
_UFRMH_FRM9_SIZE | none | 0x1 |
_UFRMH_FRM9_LENGTH | none | 0x1 |
_UFRMH_FRM9_MASK | none | 0x2 |
_UFRMH_FRM10_POSN | none | 0x2 |
_UFRMH_FRM10_POSITION | none | 0x2 |
_UFRMH_FRM10_SIZE | none | 0x1 |
_UFRMH_FRM10_LENGTH | none | 0x1 |
_UFRMH_FRM10_MASK | none | 0x4 |
_UIR_URSTIF_POSN | none | 0x0 |
_UIR_URSTIF_POSITION | none | 0x0 |
_UIR_URSTIF_SIZE | none | 0x1 |
_UIR_URSTIF_LENGTH | none | 0x1 |
_UIR_URSTIF_MASK | none | 0x1 |
_UIR_UERRIF_POSN | none | 0x1 |
_UIR_UERRIF_POSITION | none | 0x1 |
_UIR_UERRIF_SIZE | none | 0x1 |
_UIR_UERRIF_LENGTH | none | 0x1 |
_UIR_UERRIF_MASK | none | 0x2 |
_UIR_ACTVIF_POSN | none | 0x2 |
_UIR_ACTVIF_POSITION | none | 0x2 |
_UIR_ACTVIF_SIZE | none | 0x1 |
_UIR_ACTVIF_LENGTH | none | 0x1 |
_UIR_ACTVIF_MASK | none | 0x4 |
_UIR_TRNIF_POSN | none | 0x3 |
_UIR_TRNIF_POSITION | none | 0x3 |
_UIR_TRNIF_SIZE | none | 0x1 |
_UIR_TRNIF_LENGTH | none | 0x1 |
_UIR_TRNIF_MASK | none | 0x8 |
_UIR_IDLEIF_POSN | none | 0x4 |
_UIR_IDLEIF_POSITION | none | 0x4 |
_UIR_IDLEIF_SIZE | none | 0x1 |
_UIR_IDLEIF_LENGTH | none | 0x1 |
_UIR_IDLEIF_MASK | none | 0x10 |
_UIR_STALLIF_POSN | none | 0x5 |
_UIR_STALLIF_POSITION | none | 0x5 |
_UIR_STALLIF_SIZE | none | 0x1 |
_UIR_STALLIF_LENGTH | none | 0x1 |
_UIR_STALLIF_MASK | none | 0x20 |
_UIR_SOFIF_POSN | none | 0x6 |
_UIR_SOFIF_POSITION | none | 0x6 |
_UIR_SOFIF_SIZE | none | 0x1 |
_UIR_SOFIF_LENGTH | none | 0x1 |
_UIR_SOFIF_MASK | none | 0x40 |
_UIE_URSTIE_POSN | none | 0x0 |
_UIE_URSTIE_POSITION | none | 0x0 |
_UIE_URSTIE_SIZE | none | 0x1 |
_UIE_URSTIE_LENGTH | none | 0x1 |
_UIE_URSTIE_MASK | none | 0x1 |
_UIE_UERRIE_POSN | none | 0x1 |
_UIE_UERRIE_POSITION | none | 0x1 |
_UIE_UERRIE_SIZE | none | 0x1 |
_UIE_UERRIE_LENGTH | none | 0x1 |
_UIE_UERRIE_MASK | none | 0x2 |
_UIE_ACTVIE_POSN | none | 0x2 |
_UIE_ACTVIE_POSITION | none | 0x2 |
_UIE_ACTVIE_SIZE | none | 0x1 |
_UIE_ACTVIE_LENGTH | none | 0x1 |
_UIE_ACTVIE_MASK | none | 0x4 |
_UIE_TRNIE_POSN | none | 0x3 |
_UIE_TRNIE_POSITION | none | 0x3 |
_UIE_TRNIE_SIZE | none | 0x1 |
_UIE_TRNIE_LENGTH | none | 0x1 |
_UIE_TRNIE_MASK | none | 0x8 |
_UIE_IDLEIE_POSN | none | 0x4 |
_UIE_IDLEIE_POSITION | none | 0x4 |
_UIE_IDLEIE_SIZE | none | 0x1 |
_UIE_IDLEIE_LENGTH | none | 0x1 |
_UIE_IDLEIE_MASK | none | 0x10 |
_UIE_STALLIE_POSN | none | 0x5 |
_UIE_STALLIE_POSITION | none | 0x5 |
_UIE_STALLIE_SIZE | none | 0x1 |
_UIE_STALLIE_LENGTH | none | 0x1 |
_UIE_STALLIE_MASK | none | 0x20 |
_UIE_SOFIE_POSN | none | 0x6 |
_UIE_SOFIE_POSITION | none | 0x6 |
_UIE_SOFIE_SIZE | none | 0x1 |
_UIE_SOFIE_LENGTH | none | 0x1 |
_UIE_SOFIE_MASK | none | 0x40 |
_UEIR_PIDEF_POSN | none | 0x0 |
_UEIR_PIDEF_POSITION | none | 0x0 |
_UEIR_PIDEF_SIZE | none | 0x1 |
_UEIR_PIDEF_LENGTH | none | 0x1 |
_UEIR_PIDEF_MASK | none | 0x1 |
_UEIR_CRC5EF_POSN | none | 0x1 |
_UEIR_CRC5EF_POSITION | none | 0x1 |
_UEIR_CRC5EF_SIZE | none | 0x1 |
_UEIR_CRC5EF_LENGTH | none | 0x1 |
_UEIR_CRC5EF_MASK | none | 0x2 |
_UEIR_CRC16EF_POSN | none | 0x2 |
_UEIR_CRC16EF_POSITION | none | 0x2 |
_UEIR_CRC16EF_SIZE | none | 0x1 |
_UEIR_CRC16EF_LENGTH | none | 0x1 |
_UEIR_CRC16EF_MASK | none | 0x4 |
_UEIR_DFN8EF_POSN | none | 0x3 |
_UEIR_DFN8EF_POSITION | none | 0x3 |
_UEIR_DFN8EF_SIZE | none | 0x1 |
_UEIR_DFN8EF_LENGTH | none | 0x1 |
_UEIR_DFN8EF_MASK | none | 0x8 |
_UEIR_BTOEF_POSN | none | 0x4 |
_UEIR_BTOEF_POSITION | none | 0x4 |
_UEIR_BTOEF_SIZE | none | 0x1 |
_UEIR_BTOEF_LENGTH | none | 0x1 |
_UEIR_BTOEF_MASK | none | 0x10 |
_UEIR_BTSEF_POSN | none | 0x7 |
_UEIR_BTSEF_POSITION | none | 0x7 |
_UEIR_BTSEF_SIZE | none | 0x1 |
_UEIR_BTSEF_LENGTH | none | 0x1 |
_UEIR_BTSEF_MASK | none | 0x80 |
_UEIE_PIDEE_POSN | none | 0x0 |
_UEIE_PIDEE_POSITION | none | 0x0 |
_UEIE_PIDEE_SIZE | none | 0x1 |
_UEIE_PIDEE_LENGTH | none | 0x1 |
_UEIE_PIDEE_MASK | none | 0x1 |
_UEIE_CRC5EE_POSN | none | 0x1 |
_UEIE_CRC5EE_POSITION | none | 0x1 |
_UEIE_CRC5EE_SIZE | none | 0x1 |
_UEIE_CRC5EE_LENGTH | none | 0x1 |
_UEIE_CRC5EE_MASK | none | 0x2 |
_UEIE_CRC16EE_POSN | none | 0x2 |
_UEIE_CRC16EE_POSITION | none | 0x2 |
_UEIE_CRC16EE_SIZE | none | 0x1 |
_UEIE_CRC16EE_LENGTH | none | 0x1 |
_UEIE_CRC16EE_MASK | none | 0x4 |
_UEIE_DFN8EE_POSN | none | 0x3 |
_UEIE_DFN8EE_POSITION | none | 0x3 |
_UEIE_DFN8EE_SIZE | none | 0x1 |
_UEIE_DFN8EE_LENGTH | none | 0x1 |
_UEIE_DFN8EE_MASK | none | 0x8 |
_UEIE_BTOEE_POSN | none | 0x4 |
_UEIE_BTOEE_POSITION | none | 0x4 |
_UEIE_BTOEE_SIZE | none | 0x1 |
_UEIE_BTOEE_LENGTH | none | 0x1 |
_UEIE_BTOEE_MASK | none | 0x10 |
_UEIE_BTSEE_POSN | none | 0x7 |
_UEIE_BTSEE_POSITION | none | 0x7 |
_UEIE_BTSEE_SIZE | none | 0x1 |
_UEIE_BTSEE_LENGTH | none | 0x1 |
_UEIE_BTSEE_MASK | none | 0x80 |
_USTAT_PPBI_POSN | none | 0x1 |
_USTAT_PPBI_POSITION | none | 0x1 |
_USTAT_PPBI_SIZE | none | 0x1 |
_USTAT_PPBI_LENGTH | none | 0x1 |
_USTAT_PPBI_MASK | none | 0x2 |
_USTAT_DIR_POSN | none | 0x2 |
_USTAT_DIR_POSITION | none | 0x2 |
_USTAT_DIR_SIZE | none | 0x1 |
_USTAT_DIR_LENGTH | none | 0x1 |
_USTAT_DIR_MASK | none | 0x4 |
_USTAT_ENDP_POSN | none | 0x3 |
_USTAT_ENDP_POSITION | none | 0x3 |
_USTAT_ENDP_SIZE | none | 0x4 |
_USTAT_ENDP_LENGTH | none | 0x4 |
_USTAT_ENDP_MASK | none | 0x78 |
_USTAT_ENDP0_POSN | none | 0x3 |
_USTAT_ENDP0_POSITION | none | 0x3 |
_USTAT_ENDP0_SIZE | none | 0x1 |
_USTAT_ENDP0_LENGTH | none | 0x1 |
_USTAT_ENDP0_MASK | none | 0x8 |
_USTAT_ENDP1_POSN | none | 0x4 |
_USTAT_ENDP1_POSITION | none | 0x4 |
_USTAT_ENDP1_SIZE | none | 0x1 |
_USTAT_ENDP1_LENGTH | none | 0x1 |
_USTAT_ENDP1_MASK | none | 0x10 |
_USTAT_ENDP2_POSN | none | 0x5 |
_USTAT_ENDP2_POSITION | none | 0x5 |
_USTAT_ENDP2_SIZE | none | 0x1 |
_USTAT_ENDP2_LENGTH | none | 0x1 |
_USTAT_ENDP2_MASK | none | 0x20 |
_USTAT_ENDP3_POSN | none | 0x6 |
_USTAT_ENDP3_POSITION | none | 0x6 |
_USTAT_ENDP3_SIZE | none | 0x1 |
_USTAT_ENDP3_LENGTH | none | 0x1 |
_USTAT_ENDP3_MASK | none | 0x40 |
_UCON_SUSPND_POSN | none | 0x1 |
_UCON_SUSPND_POSITION | none | 0x1 |
_UCON_SUSPND_SIZE | none | 0x1 |
_UCON_SUSPND_LENGTH | none | 0x1 |
_UCON_SUSPND_MASK | none | 0x2 |
_UCON_RESUME_POSN | none | 0x2 |
_UCON_RESUME_POSITION | none | 0x2 |
_UCON_RESUME_SIZE | none | 0x1 |
_UCON_RESUME_LENGTH | none | 0x1 |
_UCON_RESUME_MASK | none | 0x4 |
_UCON_USBEN_POSN | none | 0x3 |
_UCON_USBEN_POSITION | none | 0x3 |
_UCON_USBEN_SIZE | none | 0x1 |
_UCON_USBEN_LENGTH | none | 0x1 |
_UCON_USBEN_MASK | none | 0x8 |
_UCON_PKTDIS_POSN | none | 0x4 |
_UCON_PKTDIS_POSITION | none | 0x4 |
_UCON_PKTDIS_SIZE | none | 0x1 |
_UCON_PKTDIS_LENGTH | none | 0x1 |
_UCON_PKTDIS_MASK | none | 0x10 |
_UCON_SE0_POSN | none | 0x5 |
_UCON_SE0_POSITION | none | 0x5 |
_UCON_SE0_SIZE | none | 0x1 |
_UCON_SE0_LENGTH | none | 0x1 |
_UCON_SE0_MASK | none | 0x20 |
_UCON_PPBRST_POSN | none | 0x6 |
_UCON_PPBRST_POSITION | none | 0x6 |
_UCON_PPBRST_SIZE | none | 0x1 |
_UCON_PPBRST_LENGTH | none | 0x1 |
_UCON_PPBRST_MASK | none | 0x40 |
_UADDR_ADDR_POSN | none | 0x0 |
_UADDR_ADDR_POSITION | none | 0x0 |
_UADDR_ADDR_SIZE | none | 0x7 |
_UADDR_ADDR_LENGTH | none | 0x7 |
_UADDR_ADDR_MASK | none | 0x7F |
_UADDR_ADDR0_POSN | none | 0x0 |
_UADDR_ADDR0_POSITION | none | 0x0 |
_UADDR_ADDR0_SIZE | none | 0x1 |
_UADDR_ADDR0_LENGTH | none | 0x1 |
_UADDR_ADDR0_MASK | none | 0x1 |
_UADDR_ADDR1_POSN | none | 0x1 |
_UADDR_ADDR1_POSITION | none | 0x1 |
_UADDR_ADDR1_SIZE | none | 0x1 |
_UADDR_ADDR1_LENGTH | none | 0x1 |
_UADDR_ADDR1_MASK | none | 0x2 |
_UADDR_ADDR2_POSN | none | 0x2 |
_UADDR_ADDR2_POSITION | none | 0x2 |
_UADDR_ADDR2_SIZE | none | 0x1 |
_UADDR_ADDR2_LENGTH | none | 0x1 |
_UADDR_ADDR2_MASK | none | 0x4 |
_UADDR_ADDR3_POSN | none | 0x3 |
_UADDR_ADDR3_POSITION | none | 0x3 |
_UADDR_ADDR3_SIZE | none | 0x1 |
_UADDR_ADDR3_LENGTH | none | 0x1 |
_UADDR_ADDR3_MASK | none | 0x8 |
_UADDR_ADDR4_POSN | none | 0x4 |
_UADDR_ADDR4_POSITION | none | 0x4 |
_UADDR_ADDR4_SIZE | none | 0x1 |
_UADDR_ADDR4_LENGTH | none | 0x1 |
_UADDR_ADDR4_MASK | none | 0x10 |
_UADDR_ADDR5_POSN | none | 0x5 |
_UADDR_ADDR5_POSITION | none | 0x5 |
_UADDR_ADDR5_SIZE | none | 0x1 |
_UADDR_ADDR5_LENGTH | none | 0x1 |
_UADDR_ADDR5_MASK | none | 0x20 |
_UADDR_ADDR6_POSN | none | 0x6 |
_UADDR_ADDR6_POSITION | none | 0x6 |
_UADDR_ADDR6_SIZE | none | 0x1 |
_UADDR_ADDR6_LENGTH | none | 0x1 |
_UADDR_ADDR6_MASK | none | 0x40 |
_UCFG_PPB_POSN | none | 0x0 |
_UCFG_PPB_POSITION | none | 0x0 |
_UCFG_PPB_SIZE | none | 0x2 |
_UCFG_PPB_LENGTH | none | 0x2 |
_UCFG_PPB_MASK | none | 0x3 |
_UCFG_FSEN_POSN | none | 0x2 |
_UCFG_FSEN_POSITION | none | 0x2 |
_UCFG_FSEN_SIZE | none | 0x1 |
_UCFG_FSEN_LENGTH | none | 0x1 |
_UCFG_FSEN_MASK | none | 0x4 |
_UCFG_UTRDIS_POSN | none | 0x3 |
_UCFG_UTRDIS_POSITION | none | 0x3 |
_UCFG_UTRDIS_SIZE | none | 0x1 |
_UCFG_UTRDIS_LENGTH | none | 0x1 |
_UCFG_UTRDIS_MASK | none | 0x8 |
_UCFG_UPUEN_POSN | none | 0x4 |
_UCFG_UPUEN_POSITION | none | 0x4 |
_UCFG_UPUEN_SIZE | none | 0x1 |
_UCFG_UPUEN_LENGTH | none | 0x1 |
_UCFG_UPUEN_MASK | none | 0x10 |
_UCFG_UOEMON_POSN | none | 0x6 |
_UCFG_UOEMON_POSITION | none | 0x6 |
_UCFG_UOEMON_SIZE | none | 0x1 |
_UCFG_UOEMON_LENGTH | none | 0x1 |
_UCFG_UOEMON_MASK | none | 0x40 |
_UCFG_UTEYE_POSN | none | 0x7 |
_UCFG_UTEYE_POSITION | none | 0x7 |
_UCFG_UTEYE_SIZE | none | 0x1 |
_UCFG_UTEYE_LENGTH | none | 0x1 |
_UCFG_UTEYE_MASK | none | 0x80 |
_UCFG_PPB0_POSN | none | 0x0 |
_UCFG_PPB0_POSITION | none | 0x0 |
_UCFG_PPB0_SIZE | none | 0x1 |
_UCFG_PPB0_LENGTH | none | 0x1 |
_UCFG_PPB0_MASK | none | 0x1 |
_UCFG_PPB1_POSN | none | 0x1 |
_UCFG_PPB1_POSITION | none | 0x1 |
_UCFG_PPB1_SIZE | none | 0x1 |
_UCFG_PPB1_LENGTH | none | 0x1 |
_UCFG_PPB1_MASK | none | 0x2 |
_UCFG_UPP0_POSN | none | 0x0 |
_UCFG_UPP0_POSITION | none | 0x0 |
_UCFG_UPP0_SIZE | none | 0x1 |
_UCFG_UPP0_LENGTH | none | 0x1 |
_UCFG_UPP0_MASK | none | 0x1 |
_UCFG_UPP1_POSN | none | 0x1 |
_UCFG_UPP1_POSITION | none | 0x1 |
_UCFG_UPP1_SIZE | none | 0x1 |
_UCFG_UPP1_LENGTH | none | 0x1 |
_UCFG_UPP1_MASK | none | 0x2 |
_UEP0_EPSTALL_POSN | none | 0x0 |
_UEP0_EPSTALL_POSITION | none | 0x0 |
_UEP0_EPSTALL_SIZE | none | 0x1 |
_UEP0_EPSTALL_LENGTH | none | 0x1 |
_UEP0_EPSTALL_MASK | none | 0x1 |
_UEP0_EPINEN_POSN | none | 0x1 |
_UEP0_EPINEN_POSITION | none | 0x1 |
_UEP0_EPINEN_SIZE | none | 0x1 |
_UEP0_EPINEN_LENGTH | none | 0x1 |
_UEP0_EPINEN_MASK | none | 0x2 |
_UEP0_EPOUTEN_POSN | none | 0x2 |
_UEP0_EPOUTEN_POSITION | none | 0x2 |
_UEP0_EPOUTEN_SIZE | none | 0x1 |
_UEP0_EPOUTEN_LENGTH | none | 0x1 |
_UEP0_EPOUTEN_MASK | none | 0x4 |
_UEP0_EPCONDIS_POSN | none | 0x3 |
_UEP0_EPCONDIS_POSITION | none | 0x3 |
_UEP0_EPCONDIS_SIZE | none | 0x1 |
_UEP0_EPCONDIS_LENGTH | none | 0x1 |
_UEP0_EPCONDIS_MASK | none | 0x8 |
_UEP0_EPHSHK_POSN | none | 0x4 |
_UEP0_EPHSHK_POSITION | none | 0x4 |
_UEP0_EPHSHK_SIZE | none | 0x1 |
_UEP0_EPHSHK_LENGTH | none | 0x1 |
_UEP0_EPHSHK_MASK | none | 0x10 |
_UEP0_EP0CONDIS_POSN | none | 0x3 |
_UEP0_EP0CONDIS_POSITION | none | 0x3 |
_UEP0_EP0CONDIS_SIZE | none | 0x1 |
_UEP0_EP0CONDIS_LENGTH | none | 0x1 |
_UEP0_EP0CONDIS_MASK | none | 0x8 |
_UEP0_EP0HSHK_POSN | none | 0x4 |
_UEP0_EP0HSHK_POSITION | none | 0x4 |
_UEP0_EP0HSHK_SIZE | none | 0x1 |
_UEP0_EP0HSHK_LENGTH | none | 0x1 |
_UEP0_EP0HSHK_MASK | none | 0x10 |
_UEP0_EP0INEN_POSN | none | 0x1 |
_UEP0_EP0INEN_POSITION | none | 0x1 |
_UEP0_EP0INEN_SIZE | none | 0x1 |
_UEP0_EP0INEN_LENGTH | none | 0x1 |
_UEP0_EP0INEN_MASK | none | 0x2 |
_UEP0_EP0OUTEN_POSN | none | 0x2 |
_UEP0_EP0OUTEN_POSITION | none | 0x2 |
_UEP0_EP0OUTEN_SIZE | none | 0x1 |
_UEP0_EP0OUTEN_LENGTH | none | 0x1 |
_UEP0_EP0OUTEN_MASK | none | 0x4 |
_UEP0_EP0STALL_POSN | none | 0x0 |
_UEP0_EP0STALL_POSITION | none | 0x0 |
_UEP0_EP0STALL_SIZE | none | 0x1 |
_UEP0_EP0STALL_LENGTH | none | 0x1 |
_UEP0_EP0STALL_MASK | none | 0x1 |
_UEP0_EPCONDIS0_POSN | none | 0x3 |
_UEP0_EPCONDIS0_POSITION | none | 0x3 |
_UEP0_EPCONDIS0_SIZE | none | 0x1 |
_UEP0_EPCONDIS0_LENGTH | none | 0x1 |
_UEP0_EPCONDIS0_MASK | none | 0x8 |
_UEP0_EPHSHK0_POSN | none | 0x4 |
_UEP0_EPHSHK0_POSITION | none | 0x4 |
_UEP0_EPHSHK0_SIZE | none | 0x1 |
_UEP0_EPHSHK0_LENGTH | none | 0x1 |
_UEP0_EPHSHK0_MASK | none | 0x10 |
_UEP0_EPINEN0_POSN | none | 0x1 |
_UEP0_EPINEN0_POSITION | none | 0x1 |
_UEP0_EPINEN0_SIZE | none | 0x1 |
_UEP0_EPINEN0_LENGTH | none | 0x1 |
_UEP0_EPINEN0_MASK | none | 0x2 |
_UEP0_EPOUTEN0_POSN | none | 0x2 |
_UEP0_EPOUTEN0_POSITION | none | 0x2 |
_UEP0_EPOUTEN0_SIZE | none | 0x1 |
_UEP0_EPOUTEN0_LENGTH | none | 0x1 |
_UEP0_EPOUTEN0_MASK | none | 0x4 |
_UEP0_EPSTALL0_POSN | none | 0x0 |
_UEP0_EPSTALL0_POSITION | none | 0x0 |
_UEP0_EPSTALL0_SIZE | none | 0x1 |
_UEP0_EPSTALL0_LENGTH | none | 0x1 |
_UEP0_EPSTALL0_MASK | none | 0x1 |
_UEP1_EPSTALL_POSN | none | 0x0 |
_UEP1_EPSTALL_POSITION | none | 0x0 |
_UEP1_EPSTALL_SIZE | none | 0x1 |
_UEP1_EPSTALL_LENGTH | none | 0x1 |
_UEP1_EPSTALL_MASK | none | 0x1 |
_UEP1_EPINEN_POSN | none | 0x1 |
_UEP1_EPINEN_POSITION | none | 0x1 |
_UEP1_EPINEN_SIZE | none | 0x1 |
_UEP1_EPINEN_LENGTH | none | 0x1 |
_UEP1_EPINEN_MASK | none | 0x2 |
_UEP1_EPOUTEN_POSN | none | 0x2 |
_UEP1_EPOUTEN_POSITION | none | 0x2 |
_UEP1_EPOUTEN_SIZE | none | 0x1 |
_UEP1_EPOUTEN_LENGTH | none | 0x1 |
_UEP1_EPOUTEN_MASK | none | 0x4 |
_UEP1_EPCONDIS_POSN | none | 0x3 |
_UEP1_EPCONDIS_POSITION | none | 0x3 |
_UEP1_EPCONDIS_SIZE | none | 0x1 |
_UEP1_EPCONDIS_LENGTH | none | 0x1 |
_UEP1_EPCONDIS_MASK | none | 0x8 |
_UEP1_EPHSHK_POSN | none | 0x4 |
_UEP1_EPHSHK_POSITION | none | 0x4 |
_UEP1_EPHSHK_SIZE | none | 0x1 |
_UEP1_EPHSHK_LENGTH | none | 0x1 |
_UEP1_EPHSHK_MASK | none | 0x10 |
_UEP1_EP1CONDIS_POSN | none | 0x3 |
_UEP1_EP1CONDIS_POSITION | none | 0x3 |
_UEP1_EP1CONDIS_SIZE | none | 0x1 |
_UEP1_EP1CONDIS_LENGTH | none | 0x1 |
_UEP1_EP1CONDIS_MASK | none | 0x8 |
_UEP1_EP1HSHK_POSN | none | 0x4 |
_UEP1_EP1HSHK_POSITION | none | 0x4 |
_UEP1_EP1HSHK_SIZE | none | 0x1 |
_UEP1_EP1HSHK_LENGTH | none | 0x1 |
_UEP1_EP1HSHK_MASK | none | 0x10 |
_UEP1_EP1INEN_POSN | none | 0x1 |
_UEP1_EP1INEN_POSITION | none | 0x1 |
_UEP1_EP1INEN_SIZE | none | 0x1 |
_UEP1_EP1INEN_LENGTH | none | 0x1 |
_UEP1_EP1INEN_MASK | none | 0x2 |
_UEP1_EP1OUTEN_POSN | none | 0x2 |
_UEP1_EP1OUTEN_POSITION | none | 0x2 |
_UEP1_EP1OUTEN_SIZE | none | 0x1 |
_UEP1_EP1OUTEN_LENGTH | none | 0x1 |
_UEP1_EP1OUTEN_MASK | none | 0x4 |
_UEP1_EP1STALL_POSN | none | 0x0 |
_UEP1_EP1STALL_POSITION | none | 0x0 |
_UEP1_EP1STALL_SIZE | none | 0x1 |
_UEP1_EP1STALL_LENGTH | none | 0x1 |
_UEP1_EP1STALL_MASK | none | 0x1 |
_UEP1_EPCONDIS1_POSN | none | 0x3 |
_UEP1_EPCONDIS1_POSITION | none | 0x3 |
_UEP1_EPCONDIS1_SIZE | none | 0x1 |
_UEP1_EPCONDIS1_LENGTH | none | 0x1 |
_UEP1_EPCONDIS1_MASK | none | 0x8 |
_UEP1_EPHSHK1_POSN | none | 0x4 |
_UEP1_EPHSHK1_POSITION | none | 0x4 |
_UEP1_EPHSHK1_SIZE | none | 0x1 |
_UEP1_EPHSHK1_LENGTH | none | 0x1 |
_UEP1_EPHSHK1_MASK | none | 0x10 |
_UEP1_EPINEN1_POSN | none | 0x1 |
_UEP1_EPINEN1_POSITION | none | 0x1 |
_UEP1_EPINEN1_SIZE | none | 0x1 |
_UEP1_EPINEN1_LENGTH | none | 0x1 |
_UEP1_EPINEN1_MASK | none | 0x2 |
_UEP1_EPOUTEN1_POSN | none | 0x2 |
_UEP1_EPOUTEN1_POSITION | none | 0x2 |
_UEP1_EPOUTEN1_SIZE | none | 0x1 |
_UEP1_EPOUTEN1_LENGTH | none | 0x1 |
_UEP1_EPOUTEN1_MASK | none | 0x4 |
_UEP1_EPSTALL1_POSN | none | 0x0 |
_UEP1_EPSTALL1_POSITION | none | 0x0 |
_UEP1_EPSTALL1_SIZE | none | 0x1 |
_UEP1_EPSTALL1_LENGTH | none | 0x1 |
_UEP1_EPSTALL1_MASK | none | 0x1 |
_UEP2_EPSTALL_POSN | none | 0x0 |
_UEP2_EPSTALL_POSITION | none | 0x0 |
_UEP2_EPSTALL_SIZE | none | 0x1 |
_UEP2_EPSTALL_LENGTH | none | 0x1 |
_UEP2_EPSTALL_MASK | none | 0x1 |
_UEP2_EPINEN_POSN | none | 0x1 |
_UEP2_EPINEN_POSITION | none | 0x1 |
_UEP2_EPINEN_SIZE | none | 0x1 |
_UEP2_EPINEN_LENGTH | none | 0x1 |
_UEP2_EPINEN_MASK | none | 0x2 |
_UEP2_EPOUTEN_POSN | none | 0x2 |
_UEP2_EPOUTEN_POSITION | none | 0x2 |
_UEP2_EPOUTEN_SIZE | none | 0x1 |
_UEP2_EPOUTEN_LENGTH | none | 0x1 |
_UEP2_EPOUTEN_MASK | none | 0x4 |
_UEP2_EPCONDIS_POSN | none | 0x3 |
_UEP2_EPCONDIS_POSITION | none | 0x3 |
_UEP2_EPCONDIS_SIZE | none | 0x1 |
_UEP2_EPCONDIS_LENGTH | none | 0x1 |
_UEP2_EPCONDIS_MASK | none | 0x8 |
_UEP2_EPHSHK_POSN | none | 0x4 |
_UEP2_EPHSHK_POSITION | none | 0x4 |
_UEP2_EPHSHK_SIZE | none | 0x1 |
_UEP2_EPHSHK_LENGTH | none | 0x1 |
_UEP2_EPHSHK_MASK | none | 0x10 |
_UEP2_EP2CONDIS_POSN | none | 0x3 |
_UEP2_EP2CONDIS_POSITION | none | 0x3 |
_UEP2_EP2CONDIS_SIZE | none | 0x1 |
_UEP2_EP2CONDIS_LENGTH | none | 0x1 |
_UEP2_EP2CONDIS_MASK | none | 0x8 |
_UEP2_EP2HSHK_POSN | none | 0x4 |
_UEP2_EP2HSHK_POSITION | none | 0x4 |
_UEP2_EP2HSHK_SIZE | none | 0x1 |
_UEP2_EP2HSHK_LENGTH | none | 0x1 |
_UEP2_EP2HSHK_MASK | none | 0x10 |
_UEP2_EP2INEN_POSN | none | 0x1 |
_UEP2_EP2INEN_POSITION | none | 0x1 |
_UEP2_EP2INEN_SIZE | none | 0x1 |
_UEP2_EP2INEN_LENGTH | none | 0x1 |
_UEP2_EP2INEN_MASK | none | 0x2 |
_UEP2_EP2OUTEN_POSN | none | 0x2 |
_UEP2_EP2OUTEN_POSITION | none | 0x2 |
_UEP2_EP2OUTEN_SIZE | none | 0x1 |
_UEP2_EP2OUTEN_LENGTH | none | 0x1 |
_UEP2_EP2OUTEN_MASK | none | 0x4 |
_UEP2_EP2STALL_POSN | none | 0x0 |
_UEP2_EP2STALL_POSITION | none | 0x0 |
_UEP2_EP2STALL_SIZE | none | 0x1 |
_UEP2_EP2STALL_LENGTH | none | 0x1 |
_UEP2_EP2STALL_MASK | none | 0x1 |
_UEP2_EPCONDIS2_POSN | none | 0x3 |
_UEP2_EPCONDIS2_POSITION | none | 0x3 |
_UEP2_EPCONDIS2_SIZE | none | 0x1 |
_UEP2_EPCONDIS2_LENGTH | none | 0x1 |
_UEP2_EPCONDIS2_MASK | none | 0x8 |
_UEP2_EPHSHK2_POSN | none | 0x4 |
_UEP2_EPHSHK2_POSITION | none | 0x4 |
_UEP2_EPHSHK2_SIZE | none | 0x1 |
_UEP2_EPHSHK2_LENGTH | none | 0x1 |
_UEP2_EPHSHK2_MASK | none | 0x10 |
_UEP2_EPINEN2_POSN | none | 0x1 |
_UEP2_EPINEN2_POSITION | none | 0x1 |
_UEP2_EPINEN2_SIZE | none | 0x1 |
_UEP2_EPINEN2_LENGTH | none | 0x1 |
_UEP2_EPINEN2_MASK | none | 0x2 |
_UEP2_EPOUTEN2_POSN | none | 0x2 |
_UEP2_EPOUTEN2_POSITION | none | 0x2 |
_UEP2_EPOUTEN2_SIZE | none | 0x1 |
_UEP2_EPOUTEN2_LENGTH | none | 0x1 |
_UEP2_EPOUTEN2_MASK | none | 0x4 |
_UEP2_EPSTALL2_POSN | none | 0x0 |
_UEP2_EPSTALL2_POSITION | none | 0x0 |
_UEP2_EPSTALL2_SIZE | none | 0x1 |
_UEP2_EPSTALL2_LENGTH | none | 0x1 |
_UEP2_EPSTALL2_MASK | none | 0x1 |
_UEP3_EPSTALL_POSN | none | 0x0 |
_UEP3_EPSTALL_POSITION | none | 0x0 |
_UEP3_EPSTALL_SIZE | none | 0x1 |
_UEP3_EPSTALL_LENGTH | none | 0x1 |
_UEP3_EPSTALL_MASK | none | 0x1 |
_UEP3_EPINEN_POSN | none | 0x1 |
_UEP3_EPINEN_POSITION | none | 0x1 |
_UEP3_EPINEN_SIZE | none | 0x1 |
_UEP3_EPINEN_LENGTH | none | 0x1 |
_UEP3_EPINEN_MASK | none | 0x2 |
_UEP3_EPOUTEN_POSN | none | 0x2 |
_UEP3_EPOUTEN_POSITION | none | 0x2 |
_UEP3_EPOUTEN_SIZE | none | 0x1 |
_UEP3_EPOUTEN_LENGTH | none | 0x1 |
_UEP3_EPOUTEN_MASK | none | 0x4 |
_UEP3_EPCONDIS_POSN | none | 0x3 |
_UEP3_EPCONDIS_POSITION | none | 0x3 |
_UEP3_EPCONDIS_SIZE | none | 0x1 |
_UEP3_EPCONDIS_LENGTH | none | 0x1 |
_UEP3_EPCONDIS_MASK | none | 0x8 |
_UEP3_EPHSHK_POSN | none | 0x4 |
_UEP3_EPHSHK_POSITION | none | 0x4 |
_UEP3_EPHSHK_SIZE | none | 0x1 |
_UEP3_EPHSHK_LENGTH | none | 0x1 |
_UEP3_EPHSHK_MASK | none | 0x10 |
_UEP3_EP3CONDIS_POSN | none | 0x3 |
_UEP3_EP3CONDIS_POSITION | none | 0x3 |
_UEP3_EP3CONDIS_SIZE | none | 0x1 |
_UEP3_EP3CONDIS_LENGTH | none | 0x1 |
_UEP3_EP3CONDIS_MASK | none | 0x8 |
_UEP3_EP3HSHK_POSN | none | 0x4 |
_UEP3_EP3HSHK_POSITION | none | 0x4 |
_UEP3_EP3HSHK_SIZE | none | 0x1 |
_UEP3_EP3HSHK_LENGTH | none | 0x1 |
_UEP3_EP3HSHK_MASK | none | 0x10 |
_UEP3_EP3INEN_POSN | none | 0x1 |
_UEP3_EP3INEN_POSITION | none | 0x1 |
_UEP3_EP3INEN_SIZE | none | 0x1 |
_UEP3_EP3INEN_LENGTH | none | 0x1 |
_UEP3_EP3INEN_MASK | none | 0x2 |
_UEP3_EP3OUTEN_POSN | none | 0x2 |
_UEP3_EP3OUTEN_POSITION | none | 0x2 |
_UEP3_EP3OUTEN_SIZE | none | 0x1 |
_UEP3_EP3OUTEN_LENGTH | none | 0x1 |
_UEP3_EP3OUTEN_MASK | none | 0x4 |
_UEP3_EP3STALL_POSN | none | 0x0 |
_UEP3_EP3STALL_POSITION | none | 0x0 |
_UEP3_EP3STALL_SIZE | none | 0x1 |
_UEP3_EP3STALL_LENGTH | none | 0x1 |
_UEP3_EP3STALL_MASK | none | 0x1 |
_UEP3_EPCONDIS3_POSN | none | 0x3 |
_UEP3_EPCONDIS3_POSITION | none | 0x3 |
_UEP3_EPCONDIS3_SIZE | none | 0x1 |
_UEP3_EPCONDIS3_LENGTH | none | 0x1 |
_UEP3_EPCONDIS3_MASK | none | 0x8 |
_UEP3_EPHSHK3_POSN | none | 0x4 |
_UEP3_EPHSHK3_POSITION | none | 0x4 |
_UEP3_EPHSHK3_SIZE | none | 0x1 |
_UEP3_EPHSHK3_LENGTH | none | 0x1 |
_UEP3_EPHSHK3_MASK | none | 0x10 |
_UEP3_EPINEN3_POSN | none | 0x1 |
_UEP3_EPINEN3_POSITION | none | 0x1 |
_UEP3_EPINEN3_SIZE | none | 0x1 |
_UEP3_EPINEN3_LENGTH | none | 0x1 |
_UEP3_EPINEN3_MASK | none | 0x2 |
_UEP3_EPOUTEN3_POSN | none | 0x2 |
_UEP3_EPOUTEN3_POSITION | none | 0x2 |
_UEP3_EPOUTEN3_SIZE | none | 0x1 |
_UEP3_EPOUTEN3_LENGTH | none | 0x1 |
_UEP3_EPOUTEN3_MASK | none | 0x4 |
_UEP3_EPSTALL3_POSN | none | 0x0 |
_UEP3_EPSTALL3_POSITION | none | 0x0 |
_UEP3_EPSTALL3_SIZE | none | 0x1 |
_UEP3_EPSTALL3_LENGTH | none | 0x1 |
_UEP3_EPSTALL3_MASK | none | 0x1 |
_UEP4_EPSTALL_POSN | none | 0x0 |
_UEP4_EPSTALL_POSITION | none | 0x0 |
_UEP4_EPSTALL_SIZE | none | 0x1 |
_UEP4_EPSTALL_LENGTH | none | 0x1 |
_UEP4_EPSTALL_MASK | none | 0x1 |
_UEP4_EPINEN_POSN | none | 0x1 |
_UEP4_EPINEN_POSITION | none | 0x1 |
_UEP4_EPINEN_SIZE | none | 0x1 |
_UEP4_EPINEN_LENGTH | none | 0x1 |
_UEP4_EPINEN_MASK | none | 0x2 |
_UEP4_EPOUTEN_POSN | none | 0x2 |
_UEP4_EPOUTEN_POSITION | none | 0x2 |
_UEP4_EPOUTEN_SIZE | none | 0x1 |
_UEP4_EPOUTEN_LENGTH | none | 0x1 |
_UEP4_EPOUTEN_MASK | none | 0x4 |
_UEP4_EPCONDIS_POSN | none | 0x3 |
_UEP4_EPCONDIS_POSITION | none | 0x3 |
_UEP4_EPCONDIS_SIZE | none | 0x1 |
_UEP4_EPCONDIS_LENGTH | none | 0x1 |
_UEP4_EPCONDIS_MASK | none | 0x8 |
_UEP4_EPHSHK_POSN | none | 0x4 |
_UEP4_EPHSHK_POSITION | none | 0x4 |
_UEP4_EPHSHK_SIZE | none | 0x1 |
_UEP4_EPHSHK_LENGTH | none | 0x1 |
_UEP4_EPHSHK_MASK | none | 0x10 |
_UEP4_EP4CONDIS_POSN | none | 0x3 |
_UEP4_EP4CONDIS_POSITION | none | 0x3 |
_UEP4_EP4CONDIS_SIZE | none | 0x1 |
_UEP4_EP4CONDIS_LENGTH | none | 0x1 |
_UEP4_EP4CONDIS_MASK | none | 0x8 |
_UEP4_EP4HSHK_POSN | none | 0x4 |
_UEP4_EP4HSHK_POSITION | none | 0x4 |
_UEP4_EP4HSHK_SIZE | none | 0x1 |
_UEP4_EP4HSHK_LENGTH | none | 0x1 |
_UEP4_EP4HSHK_MASK | none | 0x10 |
_UEP4_EP4INEN_POSN | none | 0x1 |
_UEP4_EP4INEN_POSITION | none | 0x1 |
_UEP4_EP4INEN_SIZE | none | 0x1 |
_UEP4_EP4INEN_LENGTH | none | 0x1 |
_UEP4_EP4INEN_MASK | none | 0x2 |
_UEP4_EP4OUTEN_POSN | none | 0x2 |
_UEP4_EP4OUTEN_POSITION | none | 0x2 |
_UEP4_EP4OUTEN_SIZE | none | 0x1 |
_UEP4_EP4OUTEN_LENGTH | none | 0x1 |
_UEP4_EP4OUTEN_MASK | none | 0x4 |
_UEP4_EP4STALL_POSN | none | 0x0 |
_UEP4_EP4STALL_POSITION | none | 0x0 |
_UEP4_EP4STALL_SIZE | none | 0x1 |
_UEP4_EP4STALL_LENGTH | none | 0x1 |
_UEP4_EP4STALL_MASK | none | 0x1 |
_UEP4_EPCONDIS4_POSN | none | 0x3 |
_UEP4_EPCONDIS4_POSITION | none | 0x3 |
_UEP4_EPCONDIS4_SIZE | none | 0x1 |
_UEP4_EPCONDIS4_LENGTH | none | 0x1 |
_UEP4_EPCONDIS4_MASK | none | 0x8 |
_UEP4_EPHSHK4_POSN | none | 0x4 |
_UEP4_EPHSHK4_POSITION | none | 0x4 |
_UEP4_EPHSHK4_SIZE | none | 0x1 |
_UEP4_EPHSHK4_LENGTH | none | 0x1 |
_UEP4_EPHSHK4_MASK | none | 0x10 |
_UEP4_EPINEN4_POSN | none | 0x1 |
_UEP4_EPINEN4_POSITION | none | 0x1 |
_UEP4_EPINEN4_SIZE | none | 0x1 |
_UEP4_EPINEN4_LENGTH | none | 0x1 |
_UEP4_EPINEN4_MASK | none | 0x2 |
_UEP4_EPOUTEN4_POSN | none | 0x2 |
_UEP4_EPOUTEN4_POSITION | none | 0x2 |
_UEP4_EPOUTEN4_SIZE | none | 0x1 |
_UEP4_EPOUTEN4_LENGTH | none | 0x1 |
_UEP4_EPOUTEN4_MASK | none | 0x4 |
_UEP4_EPSTALL4_POSN | none | 0x0 |
_UEP4_EPSTALL4_POSITION | none | 0x0 |
_UEP4_EPSTALL4_SIZE | none | 0x1 |
_UEP4_EPSTALL4_LENGTH | none | 0x1 |
_UEP4_EPSTALL4_MASK | none | 0x1 |
_UEP5_EPSTALL_POSN | none | 0x0 |
_UEP5_EPSTALL_POSITION | none | 0x0 |
_UEP5_EPSTALL_SIZE | none | 0x1 |
_UEP5_EPSTALL_LENGTH | none | 0x1 |
_UEP5_EPSTALL_MASK | none | 0x1 |
_UEP5_EPINEN_POSN | none | 0x1 |
_UEP5_EPINEN_POSITION | none | 0x1 |
_UEP5_EPINEN_SIZE | none | 0x1 |
_UEP5_EPINEN_LENGTH | none | 0x1 |
_UEP5_EPINEN_MASK | none | 0x2 |
_UEP5_EPOUTEN_POSN | none | 0x2 |
_UEP5_EPOUTEN_POSITION | none | 0x2 |
_UEP5_EPOUTEN_SIZE | none | 0x1 |
_UEP5_EPOUTEN_LENGTH | none | 0x1 |
_UEP5_EPOUTEN_MASK | none | 0x4 |
_UEP5_EPCONDIS_POSN | none | 0x3 |
_UEP5_EPCONDIS_POSITION | none | 0x3 |
_UEP5_EPCONDIS_SIZE | none | 0x1 |
_UEP5_EPCONDIS_LENGTH | none | 0x1 |
_UEP5_EPCONDIS_MASK | none | 0x8 |
_UEP5_EPHSHK_POSN | none | 0x4 |
_UEP5_EPHSHK_POSITION | none | 0x4 |
_UEP5_EPHSHK_SIZE | none | 0x1 |
_UEP5_EPHSHK_LENGTH | none | 0x1 |
_UEP5_EPHSHK_MASK | none | 0x10 |
_UEP5_EP5CONDIS_POSN | none | 0x3 |
_UEP5_EP5CONDIS_POSITION | none | 0x3 |
_UEP5_EP5CONDIS_SIZE | none | 0x1 |
_UEP5_EP5CONDIS_LENGTH | none | 0x1 |
_UEP5_EP5CONDIS_MASK | none | 0x8 |
_UEP5_EP5HSHK_POSN | none | 0x4 |
_UEP5_EP5HSHK_POSITION | none | 0x4 |
_UEP5_EP5HSHK_SIZE | none | 0x1 |
_UEP5_EP5HSHK_LENGTH | none | 0x1 |
_UEP5_EP5HSHK_MASK | none | 0x10 |
_UEP5_EP5INEN_POSN | none | 0x1 |
_UEP5_EP5INEN_POSITION | none | 0x1 |
_UEP5_EP5INEN_SIZE | none | 0x1 |
_UEP5_EP5INEN_LENGTH | none | 0x1 |
_UEP5_EP5INEN_MASK | none | 0x2 |
_UEP5_EP5OUTEN_POSN | none | 0x2 |
_UEP5_EP5OUTEN_POSITION | none | 0x2 |
_UEP5_EP5OUTEN_SIZE | none | 0x1 |
_UEP5_EP5OUTEN_LENGTH | none | 0x1 |
_UEP5_EP5OUTEN_MASK | none | 0x4 |
_UEP5_EP5STALL_POSN | none | 0x0 |
_UEP5_EP5STALL_POSITION | none | 0x0 |
_UEP5_EP5STALL_SIZE | none | 0x1 |
_UEP5_EP5STALL_LENGTH | none | 0x1 |
_UEP5_EP5STALL_MASK | none | 0x1 |
_UEP5_EPCONDIS5_POSN | none | 0x3 |
_UEP5_EPCONDIS5_POSITION | none | 0x3 |
_UEP5_EPCONDIS5_SIZE | none | 0x1 |
_UEP5_EPCONDIS5_LENGTH | none | 0x1 |
_UEP5_EPCONDIS5_MASK | none | 0x8 |
_UEP5_EPHSHK5_POSN | none | 0x4 |
_UEP5_EPHSHK5_POSITION | none | 0x4 |
_UEP5_EPHSHK5_SIZE | none | 0x1 |
_UEP5_EPHSHK5_LENGTH | none | 0x1 |
_UEP5_EPHSHK5_MASK | none | 0x10 |
_UEP5_EPINEN5_POSN | none | 0x1 |
_UEP5_EPINEN5_POSITION | none | 0x1 |
_UEP5_EPINEN5_SIZE | none | 0x1 |
_UEP5_EPINEN5_LENGTH | none | 0x1 |
_UEP5_EPINEN5_MASK | none | 0x2 |
_UEP5_EPOUTEN5_POSN | none | 0x2 |
_UEP5_EPOUTEN5_POSITION | none | 0x2 |
_UEP5_EPOUTEN5_SIZE | none | 0x1 |
_UEP5_EPOUTEN5_LENGTH | none | 0x1 |
_UEP5_EPOUTEN5_MASK | none | 0x4 |
_UEP5_EPSTALL5_POSN | none | 0x0 |
_UEP5_EPSTALL5_POSITION | none | 0x0 |
_UEP5_EPSTALL5_SIZE | none | 0x1 |
_UEP5_EPSTALL5_LENGTH | none | 0x1 |
_UEP5_EPSTALL5_MASK | none | 0x1 |
_UEP6_EPSTALL_POSN | none | 0x0 |
_UEP6_EPSTALL_POSITION | none | 0x0 |
_UEP6_EPSTALL_SIZE | none | 0x1 |
_UEP6_EPSTALL_LENGTH | none | 0x1 |
_UEP6_EPSTALL_MASK | none | 0x1 |
_UEP6_EPINEN_POSN | none | 0x1 |
_UEP6_EPINEN_POSITION | none | 0x1 |
_UEP6_EPINEN_SIZE | none | 0x1 |
_UEP6_EPINEN_LENGTH | none | 0x1 |
_UEP6_EPINEN_MASK | none | 0x2 |
_UEP6_EPOUTEN_POSN | none | 0x2 |
_UEP6_EPOUTEN_POSITION | none | 0x2 |
_UEP6_EPOUTEN_SIZE | none | 0x1 |
_UEP6_EPOUTEN_LENGTH | none | 0x1 |
_UEP6_EPOUTEN_MASK | none | 0x4 |
_UEP6_EPCONDIS_POSN | none | 0x3 |
_UEP6_EPCONDIS_POSITION | none | 0x3 |
_UEP6_EPCONDIS_SIZE | none | 0x1 |
_UEP6_EPCONDIS_LENGTH | none | 0x1 |
_UEP6_EPCONDIS_MASK | none | 0x8 |
_UEP6_EPHSHK_POSN | none | 0x4 |
_UEP6_EPHSHK_POSITION | none | 0x4 |
_UEP6_EPHSHK_SIZE | none | 0x1 |
_UEP6_EPHSHK_LENGTH | none | 0x1 |
_UEP6_EPHSHK_MASK | none | 0x10 |
_UEP6_EP6CONDIS_POSN | none | 0x3 |
_UEP6_EP6CONDIS_POSITION | none | 0x3 |
_UEP6_EP6CONDIS_SIZE | none | 0x1 |
_UEP6_EP6CONDIS_LENGTH | none | 0x1 |
_UEP6_EP6CONDIS_MASK | none | 0x8 |
_UEP6_EP6HSHK_POSN | none | 0x4 |
_UEP6_EP6HSHK_POSITION | none | 0x4 |
_UEP6_EP6HSHK_SIZE | none | 0x1 |
_UEP6_EP6HSHK_LENGTH | none | 0x1 |
_UEP6_EP6HSHK_MASK | none | 0x10 |
_UEP6_EP6INEN_POSN | none | 0x1 |
_UEP6_EP6INEN_POSITION | none | 0x1 |
_UEP6_EP6INEN_SIZE | none | 0x1 |
_UEP6_EP6INEN_LENGTH | none | 0x1 |
_UEP6_EP6INEN_MASK | none | 0x2 |
_UEP6_EP6OUTEN_POSN | none | 0x2 |
_UEP6_EP6OUTEN_POSITION | none | 0x2 |
_UEP6_EP6OUTEN_SIZE | none | 0x1 |
_UEP6_EP6OUTEN_LENGTH | none | 0x1 |
_UEP6_EP6OUTEN_MASK | none | 0x4 |
_UEP6_EP6STALL_POSN | none | 0x0 |
_UEP6_EP6STALL_POSITION | none | 0x0 |
_UEP6_EP6STALL_SIZE | none | 0x1 |
_UEP6_EP6STALL_LENGTH | none | 0x1 |
_UEP6_EP6STALL_MASK | none | 0x1 |
_UEP6_EPCONDIS6_POSN | none | 0x3 |
_UEP6_EPCONDIS6_POSITION | none | 0x3 |
_UEP6_EPCONDIS6_SIZE | none | 0x1 |
_UEP6_EPCONDIS6_LENGTH | none | 0x1 |
_UEP6_EPCONDIS6_MASK | none | 0x8 |
_UEP6_EPHSHK6_POSN | none | 0x4 |
_UEP6_EPHSHK6_POSITION | none | 0x4 |
_UEP6_EPHSHK6_SIZE | none | 0x1 |
_UEP6_EPHSHK6_LENGTH | none | 0x1 |
_UEP6_EPHSHK6_MASK | none | 0x10 |
_UEP6_EPINEN6_POSN | none | 0x1 |
_UEP6_EPINEN6_POSITION | none | 0x1 |
_UEP6_EPINEN6_SIZE | none | 0x1 |
_UEP6_EPINEN6_LENGTH | none | 0x1 |
_UEP6_EPINEN6_MASK | none | 0x2 |
_UEP6_EPOUTEN6_POSN | none | 0x2 |
_UEP6_EPOUTEN6_POSITION | none | 0x2 |
_UEP6_EPOUTEN6_SIZE | none | 0x1 |
_UEP6_EPOUTEN6_LENGTH | none | 0x1 |
_UEP6_EPOUTEN6_MASK | none | 0x4 |
_UEP6_EPSTALL6_POSN | none | 0x0 |
_UEP6_EPSTALL6_POSITION | none | 0x0 |
_UEP6_EPSTALL6_SIZE | none | 0x1 |
_UEP6_EPSTALL6_LENGTH | none | 0x1 |
_UEP6_EPSTALL6_MASK | none | 0x1 |
_UEP7_EPSTALL_POSN | none | 0x0 |
_UEP7_EPSTALL_POSITION | none | 0x0 |
_UEP7_EPSTALL_SIZE | none | 0x1 |
_UEP7_EPSTALL_LENGTH | none | 0x1 |
_UEP7_EPSTALL_MASK | none | 0x1 |
_UEP7_EPINEN_POSN | none | 0x1 |
_UEP7_EPINEN_POSITION | none | 0x1 |
_UEP7_EPINEN_SIZE | none | 0x1 |
_UEP7_EPINEN_LENGTH | none | 0x1 |
_UEP7_EPINEN_MASK | none | 0x2 |
_UEP7_EPOUTEN_POSN | none | 0x2 |
_UEP7_EPOUTEN_POSITION | none | 0x2 |
_UEP7_EPOUTEN_SIZE | none | 0x1 |
_UEP7_EPOUTEN_LENGTH | none | 0x1 |
_UEP7_EPOUTEN_MASK | none | 0x4 |
_UEP7_EPCONDIS_POSN | none | 0x3 |
_UEP7_EPCONDIS_POSITION | none | 0x3 |
_UEP7_EPCONDIS_SIZE | none | 0x1 |
_UEP7_EPCONDIS_LENGTH | none | 0x1 |
_UEP7_EPCONDIS_MASK | none | 0x8 |
_UEP7_EPHSHK_POSN | none | 0x4 |
_UEP7_EPHSHK_POSITION | none | 0x4 |
_UEP7_EPHSHK_SIZE | none | 0x1 |
_UEP7_EPHSHK_LENGTH | none | 0x1 |
_UEP7_EPHSHK_MASK | none | 0x10 |
_UEP7_EP7CONDIS_POSN | none | 0x3 |
_UEP7_EP7CONDIS_POSITION | none | 0x3 |
_UEP7_EP7CONDIS_SIZE | none | 0x1 |
_UEP7_EP7CONDIS_LENGTH | none | 0x1 |
_UEP7_EP7CONDIS_MASK | none | 0x8 |
_UEP7_EP7HSHK_POSN | none | 0x4 |
_UEP7_EP7HSHK_POSITION | none | 0x4 |
_UEP7_EP7HSHK_SIZE | none | 0x1 |
_UEP7_EP7HSHK_LENGTH | none | 0x1 |
_UEP7_EP7HSHK_MASK | none | 0x10 |
_UEP7_EP7INEN_POSN | none | 0x1 |
_UEP7_EP7INEN_POSITION | none | 0x1 |
_UEP7_EP7INEN_SIZE | none | 0x1 |
_UEP7_EP7INEN_LENGTH | none | 0x1 |
_UEP7_EP7INEN_MASK | none | 0x2 |
_UEP7_EP7OUTEN_POSN | none | 0x2 |
_UEP7_EP7OUTEN_POSITION | none | 0x2 |
_UEP7_EP7OUTEN_SIZE | none | 0x1 |
_UEP7_EP7OUTEN_LENGTH | none | 0x1 |
_UEP7_EP7OUTEN_MASK | none | 0x4 |
_UEP7_EP7STALL_POSN | none | 0x0 |
_UEP7_EP7STALL_POSITION | none | 0x0 |
_UEP7_EP7STALL_SIZE | none | 0x1 |
_UEP7_EP7STALL_LENGTH | none | 0x1 |
_UEP7_EP7STALL_MASK | none | 0x1 |
_UEP7_EPCONDIS7_POSN | none | 0x3 |
_UEP7_EPCONDIS7_POSITION | none | 0x3 |
_UEP7_EPCONDIS7_SIZE | none | 0x1 |
_UEP7_EPCONDIS7_LENGTH | none | 0x1 |
_UEP7_EPCONDIS7_MASK | none | 0x8 |
_UEP7_EPHSHK7_POSN | none | 0x4 |
_UEP7_EPHSHK7_POSITION | none | 0x4 |
_UEP7_EPHSHK7_SIZE | none | 0x1 |
_UEP7_EPHSHK7_LENGTH | none | 0x1 |
_UEP7_EPHSHK7_MASK | none | 0x10 |
_UEP7_EPINEN7_POSN | none | 0x1 |
_UEP7_EPINEN7_POSITION | none | 0x1 |
_UEP7_EPINEN7_SIZE | none | 0x1 |
_UEP7_EPINEN7_LENGTH | none | 0x1 |
_UEP7_EPINEN7_MASK | none | 0x2 |
_UEP7_EPOUTEN7_POSN | none | 0x2 |
_UEP7_EPOUTEN7_POSITION | none | 0x2 |
_UEP7_EPOUTEN7_SIZE | none | 0x1 |
_UEP7_EPOUTEN7_LENGTH | none | 0x1 |
_UEP7_EPOUTEN7_MASK | none | 0x4 |
_UEP7_EPSTALL7_POSN | none | 0x0 |
_UEP7_EPSTALL7_POSITION | none | 0x0 |
_UEP7_EPSTALL7_SIZE | none | 0x1 |
_UEP7_EPSTALL7_LENGTH | none | 0x1 |
_UEP7_EPSTALL7_MASK | none | 0x1 |
_UEP8_EPSTALL_POSN | none | 0x0 |
_UEP8_EPSTALL_POSITION | none | 0x0 |
_UEP8_EPSTALL_SIZE | none | 0x1 |
_UEP8_EPSTALL_LENGTH | none | 0x1 |
_UEP8_EPSTALL_MASK | none | 0x1 |
_UEP8_EPINEN_POSN | none | 0x1 |
_UEP8_EPINEN_POSITION | none | 0x1 |
_UEP8_EPINEN_SIZE | none | 0x1 |
_UEP8_EPINEN_LENGTH | none | 0x1 |
_UEP8_EPINEN_MASK | none | 0x2 |
_UEP8_EPOUTEN_POSN | none | 0x2 |
_UEP8_EPOUTEN_POSITION | none | 0x2 |
_UEP8_EPOUTEN_SIZE | none | 0x1 |
_UEP8_EPOUTEN_LENGTH | none | 0x1 |
_UEP8_EPOUTEN_MASK | none | 0x4 |
_UEP8_EPCONDIS_POSN | none | 0x3 |
_UEP8_EPCONDIS_POSITION | none | 0x3 |
_UEP8_EPCONDIS_SIZE | none | 0x1 |
_UEP8_EPCONDIS_LENGTH | none | 0x1 |
_UEP8_EPCONDIS_MASK | none | 0x8 |
_UEP8_EPHSHK_POSN | none | 0x4 |
_UEP8_EPHSHK_POSITION | none | 0x4 |
_UEP8_EPHSHK_SIZE | none | 0x1 |
_UEP8_EPHSHK_LENGTH | none | 0x1 |
_UEP8_EPHSHK_MASK | none | 0x10 |
_UEP8_EPCONDIS8_POSN | none | 0x3 |
_UEP8_EPCONDIS8_POSITION | none | 0x3 |
_UEP8_EPCONDIS8_SIZE | none | 0x1 |
_UEP8_EPCONDIS8_LENGTH | none | 0x1 |
_UEP8_EPCONDIS8_MASK | none | 0x8 |
_UEP8_EPHSHK8_POSN | none | 0x4 |
_UEP8_EPHSHK8_POSITION | none | 0x4 |
_UEP8_EPHSHK8_SIZE | none | 0x1 |
_UEP8_EPHSHK8_LENGTH | none | 0x1 |
_UEP8_EPHSHK8_MASK | none | 0x10 |
_UEP8_EPINEN8_POSN | none | 0x1 |
_UEP8_EPINEN8_POSITION | none | 0x1 |
_UEP8_EPINEN8_SIZE | none | 0x1 |
_UEP8_EPINEN8_LENGTH | none | 0x1 |
_UEP8_EPINEN8_MASK | none | 0x2 |
_UEP8_EPOUTEN8_POSN | none | 0x2 |
_UEP8_EPOUTEN8_POSITION | none | 0x2 |
_UEP8_EPOUTEN8_SIZE | none | 0x1 |
_UEP8_EPOUTEN8_LENGTH | none | 0x1 |
_UEP8_EPOUTEN8_MASK | none | 0x4 |
_UEP8_EPSTALL8_POSN | none | 0x0 |
_UEP8_EPSTALL8_POSITION | none | 0x0 |
_UEP8_EPSTALL8_SIZE | none | 0x1 |
_UEP8_EPSTALL8_LENGTH | none | 0x1 |
_UEP8_EPSTALL8_MASK | none | 0x1 |
_UEP9_EPSTALL_POSN | none | 0x0 |
_UEP9_EPSTALL_POSITION | none | 0x0 |
_UEP9_EPSTALL_SIZE | none | 0x1 |
_UEP9_EPSTALL_LENGTH | none | 0x1 |
_UEP9_EPSTALL_MASK | none | 0x1 |
_UEP9_EPINEN_POSN | none | 0x1 |
_UEP9_EPINEN_POSITION | none | 0x1 |
_UEP9_EPINEN_SIZE | none | 0x1 |
_UEP9_EPINEN_LENGTH | none | 0x1 |
_UEP9_EPINEN_MASK | none | 0x2 |
_UEP9_EPOUTEN_POSN | none | 0x2 |
_UEP9_EPOUTEN_POSITION | none | 0x2 |
_UEP9_EPOUTEN_SIZE | none | 0x1 |
_UEP9_EPOUTEN_LENGTH | none | 0x1 |
_UEP9_EPOUTEN_MASK | none | 0x4 |
_UEP9_EPCONDIS_POSN | none | 0x3 |
_UEP9_EPCONDIS_POSITION | none | 0x3 |
_UEP9_EPCONDIS_SIZE | none | 0x1 |
_UEP9_EPCONDIS_LENGTH | none | 0x1 |
_UEP9_EPCONDIS_MASK | none | 0x8 |
_UEP9_EPHSHK_POSN | none | 0x4 |
_UEP9_EPHSHK_POSITION | none | 0x4 |
_UEP9_EPHSHK_SIZE | none | 0x1 |
_UEP9_EPHSHK_LENGTH | none | 0x1 |
_UEP9_EPHSHK_MASK | none | 0x10 |
_UEP9_EPCONDIS9_POSN | none | 0x3 |
_UEP9_EPCONDIS9_POSITION | none | 0x3 |
_UEP9_EPCONDIS9_SIZE | none | 0x1 |
_UEP9_EPCONDIS9_LENGTH | none | 0x1 |
_UEP9_EPCONDIS9_MASK | none | 0x8 |
_UEP9_EPHSHK9_POSN | none | 0x4 |
_UEP9_EPHSHK9_POSITION | none | 0x4 |
_UEP9_EPHSHK9_SIZE | none | 0x1 |
_UEP9_EPHSHK9_LENGTH | none | 0x1 |
_UEP9_EPHSHK9_MASK | none | 0x10 |
_UEP9_EPINEN9_POSN | none | 0x1 |
_UEP9_EPINEN9_POSITION | none | 0x1 |
_UEP9_EPINEN9_SIZE | none | 0x1 |
_UEP9_EPINEN9_LENGTH | none | 0x1 |
_UEP9_EPINEN9_MASK | none | 0x2 |
_UEP9_EPOUTEN9_POSN | none | 0x2 |
_UEP9_EPOUTEN9_POSITION | none | 0x2 |
_UEP9_EPOUTEN9_SIZE | none | 0x1 |
_UEP9_EPOUTEN9_LENGTH | none | 0x1 |
_UEP9_EPOUTEN9_MASK | none | 0x4 |
_UEP9_EPSTALL9_POSN | none | 0x0 |
_UEP9_EPSTALL9_POSITION | none | 0x0 |
_UEP9_EPSTALL9_SIZE | none | 0x1 |
_UEP9_EPSTALL9_LENGTH | none | 0x1 |
_UEP9_EPSTALL9_MASK | none | 0x1 |
_UEP10_EPSTALL_POSN | none | 0x0 |
_UEP10_EPSTALL_POSITION | none | 0x0 |
_UEP10_EPSTALL_SIZE | none | 0x1 |
_UEP10_EPSTALL_LENGTH | none | 0x1 |
_UEP10_EPSTALL_MASK | none | 0x1 |
_UEP10_EPINEN_POSN | none | 0x1 |
_UEP10_EPINEN_POSITION | none | 0x1 |
_UEP10_EPINEN_SIZE | none | 0x1 |
_UEP10_EPINEN_LENGTH | none | 0x1 |
_UEP10_EPINEN_MASK | none | 0x2 |
_UEP10_EPOUTEN_POSN | none | 0x2 |
_UEP10_EPOUTEN_POSITION | none | 0x2 |
_UEP10_EPOUTEN_SIZE | none | 0x1 |
_UEP10_EPOUTEN_LENGTH | none | 0x1 |
_UEP10_EPOUTEN_MASK | none | 0x4 |
_UEP10_EPCONDIS_POSN | none | 0x3 |
_UEP10_EPCONDIS_POSITION | none | 0x3 |
_UEP10_EPCONDIS_SIZE | none | 0x1 |
_UEP10_EPCONDIS_LENGTH | none | 0x1 |
_UEP10_EPCONDIS_MASK | none | 0x8 |
_UEP10_EPHSHK_POSN | none | 0x4 |
_UEP10_EPHSHK_POSITION | none | 0x4 |
_UEP10_EPHSHK_SIZE | none | 0x1 |
_UEP10_EPHSHK_LENGTH | none | 0x1 |
_UEP10_EPHSHK_MASK | none | 0x10 |
_UEP10_EPCONDIS10_POSN | none | 0x3 |
_UEP10_EPCONDIS10_POSITION | none | 0x3 |
_UEP10_EPCONDIS10_SIZE | none | 0x1 |
_UEP10_EPCONDIS10_LENGTH | none | 0x1 |
_UEP10_EPCONDIS10_MASK | none | 0x8 |
_UEP10_EPHSHK10_POSN | none | 0x4 |
_UEP10_EPHSHK10_POSITION | none | 0x4 |
_UEP10_EPHSHK10_SIZE | none | 0x1 |
_UEP10_EPHSHK10_LENGTH | none | 0x1 |
_UEP10_EPHSHK10_MASK | none | 0x10 |
_UEP10_EPINEN10_POSN | none | 0x1 |
_UEP10_EPINEN10_POSITION | none | 0x1 |
_UEP10_EPINEN10_SIZE | none | 0x1 |
_UEP10_EPINEN10_LENGTH | none | 0x1 |
_UEP10_EPINEN10_MASK | none | 0x2 |
_UEP10_EPOUTEN10_POSN | none | 0x2 |
_UEP10_EPOUTEN10_POSITION | none | 0x2 |
_UEP10_EPOUTEN10_SIZE | none | 0x1 |
_UEP10_EPOUTEN10_LENGTH | none | 0x1 |
_UEP10_EPOUTEN10_MASK | none | 0x4 |
_UEP10_EPSTALL10_POSN | none | 0x0 |
_UEP10_EPSTALL10_POSITION | none | 0x0 |
_UEP10_EPSTALL10_SIZE | none | 0x1 |
_UEP10_EPSTALL10_LENGTH | none | 0x1 |
_UEP10_EPSTALL10_MASK | none | 0x1 |
_UEP11_EPSTALL_POSN | none | 0x0 |
_UEP11_EPSTALL_POSITION | none | 0x0 |
_UEP11_EPSTALL_SIZE | none | 0x1 |
_UEP11_EPSTALL_LENGTH | none | 0x1 |
_UEP11_EPSTALL_MASK | none | 0x1 |
_UEP11_EPINEN_POSN | none | 0x1 |
_UEP11_EPINEN_POSITION | none | 0x1 |
_UEP11_EPINEN_SIZE | none | 0x1 |
_UEP11_EPINEN_LENGTH | none | 0x1 |
_UEP11_EPINEN_MASK | none | 0x2 |
_UEP11_EPOUTEN_POSN | none | 0x2 |
_UEP11_EPOUTEN_POSITION | none | 0x2 |
_UEP11_EPOUTEN_SIZE | none | 0x1 |
_UEP11_EPOUTEN_LENGTH | none | 0x1 |
_UEP11_EPOUTEN_MASK | none | 0x4 |
_UEP11_EPCONDIS_POSN | none | 0x3 |
_UEP11_EPCONDIS_POSITION | none | 0x3 |
_UEP11_EPCONDIS_SIZE | none | 0x1 |
_UEP11_EPCONDIS_LENGTH | none | 0x1 |
_UEP11_EPCONDIS_MASK | none | 0x8 |
_UEP11_EPHSHK_POSN | none | 0x4 |
_UEP11_EPHSHK_POSITION | none | 0x4 |
_UEP11_EPHSHK_SIZE | none | 0x1 |
_UEP11_EPHSHK_LENGTH | none | 0x1 |
_UEP11_EPHSHK_MASK | none | 0x10 |
_UEP11_EPCONDIS11_POSN | none | 0x3 |
_UEP11_EPCONDIS11_POSITION | none | 0x3 |
_UEP11_EPCONDIS11_SIZE | none | 0x1 |
_UEP11_EPCONDIS11_LENGTH | none | 0x1 |
_UEP11_EPCONDIS11_MASK | none | 0x8 |
_UEP11_EPHSHK11_POSN | none | 0x4 |
_UEP11_EPHSHK11_POSITION | none | 0x4 |
_UEP11_EPHSHK11_SIZE | none | 0x1 |
_UEP11_EPHSHK11_LENGTH | none | 0x1 |
_UEP11_EPHSHK11_MASK | none | 0x10 |
_UEP11_EPINEN11_POSN | none | 0x1 |
_UEP11_EPINEN11_POSITION | none | 0x1 |
_UEP11_EPINEN11_SIZE | none | 0x1 |
_UEP11_EPINEN11_LENGTH | none | 0x1 |
_UEP11_EPINEN11_MASK | none | 0x2 |
_UEP11_EPOUTEN11_POSN | none | 0x2 |
_UEP11_EPOUTEN11_POSITION | none | 0x2 |
_UEP11_EPOUTEN11_SIZE | none | 0x1 |
_UEP11_EPOUTEN11_LENGTH | none | 0x1 |
_UEP11_EPOUTEN11_MASK | none | 0x4 |
_UEP11_EPSTALL11_POSN | none | 0x0 |
_UEP11_EPSTALL11_POSITION | none | 0x0 |
_UEP11_EPSTALL11_SIZE | none | 0x1 |
_UEP11_EPSTALL11_LENGTH | none | 0x1 |
_UEP11_EPSTALL11_MASK | none | 0x1 |
_UEP12_EPSTALL_POSN | none | 0x0 |
_UEP12_EPSTALL_POSITION | none | 0x0 |
_UEP12_EPSTALL_SIZE | none | 0x1 |
_UEP12_EPSTALL_LENGTH | none | 0x1 |
_UEP12_EPSTALL_MASK | none | 0x1 |
_UEP12_EPINEN_POSN | none | 0x1 |
_UEP12_EPINEN_POSITION | none | 0x1 |
_UEP12_EPINEN_SIZE | none | 0x1 |
_UEP12_EPINEN_LENGTH | none | 0x1 |
_UEP12_EPINEN_MASK | none | 0x2 |
_UEP12_EPOUTEN_POSN | none | 0x2 |
_UEP12_EPOUTEN_POSITION | none | 0x2 |
_UEP12_EPOUTEN_SIZE | none | 0x1 |
_UEP12_EPOUTEN_LENGTH | none | 0x1 |
_UEP12_EPOUTEN_MASK | none | 0x4 |
_UEP12_EPCONDIS_POSN | none | 0x3 |
_UEP12_EPCONDIS_POSITION | none | 0x3 |
_UEP12_EPCONDIS_SIZE | none | 0x1 |
_UEP12_EPCONDIS_LENGTH | none | 0x1 |
_UEP12_EPCONDIS_MASK | none | 0x8 |
_UEP12_EPHSHK_POSN | none | 0x4 |
_UEP12_EPHSHK_POSITION | none | 0x4 |
_UEP12_EPHSHK_SIZE | none | 0x1 |
_UEP12_EPHSHK_LENGTH | none | 0x1 |
_UEP12_EPHSHK_MASK | none | 0x10 |
_UEP12_EPCONDIS12_POSN | none | 0x3 |
_UEP12_EPCONDIS12_POSITION | none | 0x3 |
_UEP12_EPCONDIS12_SIZE | none | 0x1 |
_UEP12_EPCONDIS12_LENGTH | none | 0x1 |
_UEP12_EPCONDIS12_MASK | none | 0x8 |
_UEP12_EPHSHK12_POSN | none | 0x4 |
_UEP12_EPHSHK12_POSITION | none | 0x4 |
_UEP12_EPHSHK12_SIZE | none | 0x1 |
_UEP12_EPHSHK12_LENGTH | none | 0x1 |
_UEP12_EPHSHK12_MASK | none | 0x10 |
_UEP12_EPINEN12_POSN | none | 0x1 |
_UEP12_EPINEN12_POSITION | none | 0x1 |
_UEP12_EPINEN12_SIZE | none | 0x1 |
_UEP12_EPINEN12_LENGTH | none | 0x1 |
_UEP12_EPINEN12_MASK | none | 0x2 |
_UEP12_EPOUTEN12_POSN | none | 0x2 |
_UEP12_EPOUTEN12_POSITION | none | 0x2 |
_UEP12_EPOUTEN12_SIZE | none | 0x1 |
_UEP12_EPOUTEN12_LENGTH | none | 0x1 |
_UEP12_EPOUTEN12_MASK | none | 0x4 |
_UEP12_EPSTALL12_POSN | none | 0x0 |
_UEP12_EPSTALL12_POSITION | none | 0x0 |
_UEP12_EPSTALL12_SIZE | none | 0x1 |
_UEP12_EPSTALL12_LENGTH | none | 0x1 |
_UEP12_EPSTALL12_MASK | none | 0x1 |
_UEP13_EPSTALL_POSN | none | 0x0 |
_UEP13_EPSTALL_POSITION | none | 0x0 |
_UEP13_EPSTALL_SIZE | none | 0x1 |
_UEP13_EPSTALL_LENGTH | none | 0x1 |
_UEP13_EPSTALL_MASK | none | 0x1 |
_UEP13_EPINEN_POSN | none | 0x1 |
_UEP13_EPINEN_POSITION | none | 0x1 |
_UEP13_EPINEN_SIZE | none | 0x1 |
_UEP13_EPINEN_LENGTH | none | 0x1 |
_UEP13_EPINEN_MASK | none | 0x2 |
_UEP13_EPOUTEN_POSN | none | 0x2 |
_UEP13_EPOUTEN_POSITION | none | 0x2 |
_UEP13_EPOUTEN_SIZE | none | 0x1 |
_UEP13_EPOUTEN_LENGTH | none | 0x1 |
_UEP13_EPOUTEN_MASK | none | 0x4 |
_UEP13_EPCONDIS_POSN | none | 0x3 |
_UEP13_EPCONDIS_POSITION | none | 0x3 |
_UEP13_EPCONDIS_SIZE | none | 0x1 |
_UEP13_EPCONDIS_LENGTH | none | 0x1 |
_UEP13_EPCONDIS_MASK | none | 0x8 |
_UEP13_EPHSHK_POSN | none | 0x4 |
_UEP13_EPHSHK_POSITION | none | 0x4 |
_UEP13_EPHSHK_SIZE | none | 0x1 |
_UEP13_EPHSHK_LENGTH | none | 0x1 |
_UEP13_EPHSHK_MASK | none | 0x10 |
_UEP13_EPCONDIS13_POSN | none | 0x3 |
_UEP13_EPCONDIS13_POSITION | none | 0x3 |
_UEP13_EPCONDIS13_SIZE | none | 0x1 |
_UEP13_EPCONDIS13_LENGTH | none | 0x1 |
_UEP13_EPCONDIS13_MASK | none | 0x8 |
_UEP13_EPHSHK13_POSN | none | 0x4 |
_UEP13_EPHSHK13_POSITION | none | 0x4 |
_UEP13_EPHSHK13_SIZE | none | 0x1 |
_UEP13_EPHSHK13_LENGTH | none | 0x1 |
_UEP13_EPHSHK13_MASK | none | 0x10 |
_UEP13_EPINEN13_POSN | none | 0x1 |
_UEP13_EPINEN13_POSITION | none | 0x1 |
_UEP13_EPINEN13_SIZE | none | 0x1 |
_UEP13_EPINEN13_LENGTH | none | 0x1 |
_UEP13_EPINEN13_MASK | none | 0x2 |
_UEP13_EPOUTEN13_POSN | none | 0x2 |
_UEP13_EPOUTEN13_POSITION | none | 0x2 |
_UEP13_EPOUTEN13_SIZE | none | 0x1 |
_UEP13_EPOUTEN13_LENGTH | none | 0x1 |
_UEP13_EPOUTEN13_MASK | none | 0x4 |
_UEP13_EPSTALL13_POSN | none | 0x0 |
_UEP13_EPSTALL13_POSITION | none | 0x0 |
_UEP13_EPSTALL13_SIZE | none | 0x1 |
_UEP13_EPSTALL13_LENGTH | none | 0x1 |
_UEP13_EPSTALL13_MASK | none | 0x1 |
_UEP14_EPSTALL_POSN | none | 0x0 |
_UEP14_EPSTALL_POSITION | none | 0x0 |
_UEP14_EPSTALL_SIZE | none | 0x1 |
_UEP14_EPSTALL_LENGTH | none | 0x1 |
_UEP14_EPSTALL_MASK | none | 0x1 |
_UEP14_EPINEN_POSN | none | 0x1 |
_UEP14_EPINEN_POSITION | none | 0x1 |
_UEP14_EPINEN_SIZE | none | 0x1 |
_UEP14_EPINEN_LENGTH | none | 0x1 |
_UEP14_EPINEN_MASK | none | 0x2 |
_UEP14_EPOUTEN_POSN | none | 0x2 |
_UEP14_EPOUTEN_POSITION | none | 0x2 |
_UEP14_EPOUTEN_SIZE | none | 0x1 |
_UEP14_EPOUTEN_LENGTH | none | 0x1 |
_UEP14_EPOUTEN_MASK | none | 0x4 |
_UEP14_EPCONDIS_POSN | none | 0x3 |
_UEP14_EPCONDIS_POSITION | none | 0x3 |
_UEP14_EPCONDIS_SIZE | none | 0x1 |
_UEP14_EPCONDIS_LENGTH | none | 0x1 |
_UEP14_EPCONDIS_MASK | none | 0x8 |
_UEP14_EPHSHK_POSN | none | 0x4 |
_UEP14_EPHSHK_POSITION | none | 0x4 |
_UEP14_EPHSHK_SIZE | none | 0x1 |
_UEP14_EPHSHK_LENGTH | none | 0x1 |
_UEP14_EPHSHK_MASK | none | 0x10 |
_UEP14_EPCONDIS14_POSN | none | 0x3 |
_UEP14_EPCONDIS14_POSITION | none | 0x3 |
_UEP14_EPCONDIS14_SIZE | none | 0x1 |
_UEP14_EPCONDIS14_LENGTH | none | 0x1 |
_UEP14_EPCONDIS14_MASK | none | 0x8 |
_UEP14_EPHSHK14_POSN | none | 0x4 |
_UEP14_EPHSHK14_POSITION | none | 0x4 |
_UEP14_EPHSHK14_SIZE | none | 0x1 |
_UEP14_EPHSHK14_LENGTH | none | 0x1 |
_UEP14_EPHSHK14_MASK | none | 0x10 |
_UEP14_EPINEN14_POSN | none | 0x1 |
_UEP14_EPINEN14_POSITION | none | 0x1 |
_UEP14_EPINEN14_SIZE | none | 0x1 |
_UEP14_EPINEN14_LENGTH | none | 0x1 |
_UEP14_EPINEN14_MASK | none | 0x2 |
_UEP14_EPOUTEN14_POSN | none | 0x2 |
_UEP14_EPOUTEN14_POSITION | none | 0x2 |
_UEP14_EPOUTEN14_SIZE | none | 0x1 |
_UEP14_EPOUTEN14_LENGTH | none | 0x1 |
_UEP14_EPOUTEN14_MASK | none | 0x4 |
_UEP14_EPSTALL14_POSN | none | 0x0 |
_UEP14_EPSTALL14_POSITION | none | 0x0 |
_UEP14_EPSTALL14_SIZE | none | 0x1 |
_UEP14_EPSTALL14_LENGTH | none | 0x1 |
_UEP14_EPSTALL14_MASK | none | 0x1 |
_UEP15_EPSTALL_POSN | none | 0x0 |
_UEP15_EPSTALL_POSITION | none | 0x0 |
_UEP15_EPSTALL_SIZE | none | 0x1 |
_UEP15_EPSTALL_LENGTH | none | 0x1 |
_UEP15_EPSTALL_MASK | none | 0x1 |
_UEP15_EPINEN_POSN | none | 0x1 |
_UEP15_EPINEN_POSITION | none | 0x1 |
_UEP15_EPINEN_SIZE | none | 0x1 |
_UEP15_EPINEN_LENGTH | none | 0x1 |
_UEP15_EPINEN_MASK | none | 0x2 |
_UEP15_EPOUTEN_POSN | none | 0x2 |
_UEP15_EPOUTEN_POSITION | none | 0x2 |
_UEP15_EPOUTEN_SIZE | none | 0x1 |
_UEP15_EPOUTEN_LENGTH | none | 0x1 |
_UEP15_EPOUTEN_MASK | none | 0x4 |
_UEP15_EPCONDIS_POSN | none | 0x3 |
_UEP15_EPCONDIS_POSITION | none | 0x3 |
_UEP15_EPCONDIS_SIZE | none | 0x1 |
_UEP15_EPCONDIS_LENGTH | none | 0x1 |
_UEP15_EPCONDIS_MASK | none | 0x8 |
_UEP15_EPHSHK_POSN | none | 0x4 |
_UEP15_EPHSHK_POSITION | none | 0x4 |
_UEP15_EPHSHK_SIZE | none | 0x1 |
_UEP15_EPHSHK_LENGTH | none | 0x1 |
_UEP15_EPHSHK_MASK | none | 0x10 |
_UEP15_EPCONDIS15_POSN | none | 0x3 |
_UEP15_EPCONDIS15_POSITION | none | 0x3 |
_UEP15_EPCONDIS15_SIZE | none | 0x1 |
_UEP15_EPCONDIS15_LENGTH | none | 0x1 |
_UEP15_EPCONDIS15_MASK | none | 0x8 |
_UEP15_EPHSHK15_POSN | none | 0x4 |
_UEP15_EPHSHK15_POSITION | none | 0x4 |
_UEP15_EPHSHK15_SIZE | none | 0x1 |
_UEP15_EPHSHK15_LENGTH | none | 0x1 |
_UEP15_EPHSHK15_MASK | none | 0x10 |
_UEP15_EPINEN15_POSN | none | 0x1 |
_UEP15_EPINEN15_POSITION | none | 0x1 |
_UEP15_EPINEN15_SIZE | none | 0x1 |
_UEP15_EPINEN15_LENGTH | none | 0x1 |
_UEP15_EPINEN15_MASK | none | 0x2 |
_UEP15_EPOUTEN15_POSN | none | 0x2 |
_UEP15_EPOUTEN15_POSITION | none | 0x2 |
_UEP15_EPOUTEN15_SIZE | none | 0x1 |
_UEP15_EPOUTEN15_LENGTH | none | 0x1 |
_UEP15_EPOUTEN15_MASK | none | 0x4 |
_UEP15_EPSTALL15_POSN | none | 0x0 |
_UEP15_EPSTALL15_POSITION | none | 0x0 |
_UEP15_EPSTALL15_SIZE | none | 0x1 |
_UEP15_EPSTALL15_LENGTH | none | 0x1 |
_UEP15_EPSTALL15_MASK | none | 0x1 |
_PORTA_RA0_POSN | none | 0x0 |
_PORTA_RA0_POSITION | none | 0x0 |
_PORTA_RA0_SIZE | none | 0x1 |
_PORTA_RA0_LENGTH | none | 0x1 |
_PORTA_RA0_MASK | none | 0x1 |
_PORTA_RA1_POSN | none | 0x1 |
_PORTA_RA1_POSITION | none | 0x1 |
_PORTA_RA1_SIZE | none | 0x1 |
_PORTA_RA1_LENGTH | none | 0x1 |
_PORTA_RA1_MASK | none | 0x2 |
_PORTA_RA2_POSN | none | 0x2 |
_PORTA_RA2_POSITION | none | 0x2 |
_PORTA_RA2_SIZE | none | 0x1 |
_PORTA_RA2_LENGTH | none | 0x1 |
_PORTA_RA2_MASK | none | 0x4 |
_PORTA_RA3_POSN | none | 0x3 |
_PORTA_RA3_POSITION | none | 0x3 |
_PORTA_RA3_SIZE | none | 0x1 |
_PORTA_RA3_LENGTH | none | 0x1 |
_PORTA_RA3_MASK | none | 0x8 |
_PORTA_RA4_POSN | none | 0x4 |
_PORTA_RA4_POSITION | none | 0x4 |
_PORTA_RA4_SIZE | none | 0x1 |
_PORTA_RA4_LENGTH | none | 0x1 |
_PORTA_RA4_MASK | none | 0x10 |
_PORTA_RA5_POSN | none | 0x5 |
_PORTA_RA5_POSITION | none | 0x5 |
_PORTA_RA5_SIZE | none | 0x1 |
_PORTA_RA5_LENGTH | none | 0x1 |
_PORTA_RA5_MASK | none | 0x20 |
_PORTA_RA6_POSN | none | 0x6 |
_PORTA_RA6_POSITION | none | 0x6 |
_PORTA_RA6_SIZE | none | 0x1 |
_PORTA_RA6_LENGTH | none | 0x1 |
_PORTA_RA6_MASK | none | 0x40 |
_PORTA_AN0_POSN | none | 0x0 |
_PORTA_AN0_POSITION | none | 0x0 |
_PORTA_AN0_SIZE | none | 0x1 |
_PORTA_AN0_LENGTH | none | 0x1 |
_PORTA_AN0_MASK | none | 0x1 |
_PORTA_AN1_POSN | none | 0x1 |
_PORTA_AN1_POSITION | none | 0x1 |
_PORTA_AN1_SIZE | none | 0x1 |
_PORTA_AN1_LENGTH | none | 0x1 |
_PORTA_AN1_MASK | none | 0x2 |
_PORTA_AN2_POSN | none | 0x2 |
_PORTA_AN2_POSITION | none | 0x2 |
_PORTA_AN2_SIZE | none | 0x1 |
_PORTA_AN2_LENGTH | none | 0x1 |
_PORTA_AN2_MASK | none | 0x4 |
_PORTA_AN3_POSN | none | 0x3 |
_PORTA_AN3_POSITION | none | 0x3 |
_PORTA_AN3_SIZE | none | 0x1 |
_PORTA_AN3_LENGTH | none | 0x1 |
_PORTA_AN3_MASK | none | 0x8 |
_PORTA_T0CKI_POSN | none | 0x4 |
_PORTA_T0CKI_POSITION | none | 0x4 |
_PORTA_T0CKI_SIZE | none | 0x1 |
_PORTA_T0CKI_LENGTH | none | 0x1 |
_PORTA_T0CKI_MASK | none | 0x10 |
_PORTA_AN4_POSN | none | 0x5 |
_PORTA_AN4_POSITION | none | 0x5 |
_PORTA_AN4_SIZE | none | 0x1 |
_PORTA_AN4_LENGTH | none | 0x1 |
_PORTA_AN4_MASK | none | 0x20 |
_PORTA_OSC2_POSN | none | 0x6 |
_PORTA_OSC2_POSITION | none | 0x6 |
_PORTA_OSC2_SIZE | none | 0x1 |
_PORTA_OSC2_LENGTH | none | 0x1 |
_PORTA_OSC2_MASK | none | 0x40 |
_PORTA_VREFM_POSN | none | 0x2 |
_PORTA_VREFM_POSITION | none | 0x2 |
_PORTA_VREFM_SIZE | none | 0x1 |
_PORTA_VREFM_LENGTH | none | 0x1 |
_PORTA_VREFM_MASK | none | 0x4 |
_PORTA_VREFP_POSN | none | 0x3 |
_PORTA_VREFP_POSITION | none | 0x3 |
_PORTA_VREFP_SIZE | none | 0x1 |
_PORTA_VREFP_LENGTH | none | 0x1 |
_PORTA_VREFP_MASK | none | 0x8 |
_PORTA_LVDIN_POSN | none | 0x5 |
_PORTA_LVDIN_POSITION | none | 0x5 |
_PORTA_LVDIN_SIZE | none | 0x1 |
_PORTA_LVDIN_LENGTH | none | 0x1 |
_PORTA_LVDIN_MASK | none | 0x20 |
_PORTA_HLVDIN_POSN | none | 0x5 |
_PORTA_HLVDIN_POSITION | none | 0x5 |
_PORTA_HLVDIN_SIZE | none | 0x1 |
_PORTA_HLVDIN_LENGTH | none | 0x1 |
_PORTA_HLVDIN_MASK | none | 0x20 |
_PORTA_RA7_POSN | none | 0x7 |
_PORTA_RA7_POSITION | none | 0x7 |
_PORTA_RA7_SIZE | none | 0x1 |
_PORTA_RA7_LENGTH | none | 0x1 |
_PORTA_RA7_MASK | none | 0x80 |
_PORTA_RJPU_POSN | none | 0x7 |
_PORTA_RJPU_POSITION | none | 0x7 |
_PORTA_RJPU_SIZE | none | 0x1 |
_PORTA_RJPU_LENGTH | none | 0x1 |
_PORTA_RJPU_MASK | none | 0x80 |
_PORTA_ULPWUIN_POSN | none | 0x0 |
_PORTA_ULPWUIN_POSITION | none | 0x0 |
_PORTA_ULPWUIN_SIZE | none | 0x1 |
_PORTA_ULPWUIN_LENGTH | none | 0x1 |
_PORTA_ULPWUIN_MASK | none | 0x1 |
_PORTB_RB0_POSN | none | 0x0 |
_PORTB_RB0_POSITION | none | 0x0 |
_PORTB_RB0_SIZE | none | 0x1 |
_PORTB_RB0_LENGTH | none | 0x1 |
_PORTB_RB0_MASK | none | 0x1 |
_PORTB_RB1_POSN | none | 0x1 |
_PORTB_RB1_POSITION | none | 0x1 |
_PORTB_RB1_SIZE | none | 0x1 |
_PORTB_RB1_LENGTH | none | 0x1 |
_PORTB_RB1_MASK | none | 0x2 |
_PORTB_RB2_POSN | none | 0x2 |
_PORTB_RB2_POSITION | none | 0x2 |
_PORTB_RB2_SIZE | none | 0x1 |
_PORTB_RB2_LENGTH | none | 0x1 |
_PORTB_RB2_MASK | none | 0x4 |
_PORTB_RB3_POSN | none | 0x3 |
_PORTB_RB3_POSITION | none | 0x3 |
_PORTB_RB3_SIZE | none | 0x1 |
_PORTB_RB3_LENGTH | none | 0x1 |
_PORTB_RB3_MASK | none | 0x8 |
_PORTB_RB4_POSN | none | 0x4 |
_PORTB_RB4_POSITION | none | 0x4 |
_PORTB_RB4_SIZE | none | 0x1 |
_PORTB_RB4_LENGTH | none | 0x1 |
_PORTB_RB4_MASK | none | 0x10 |
_PORTB_RB5_POSN | none | 0x5 |
_PORTB_RB5_POSITION | none | 0x5 |
_PORTB_RB5_SIZE | none | 0x1 |
_PORTB_RB5_LENGTH | none | 0x1 |
_PORTB_RB5_MASK | none | 0x20 |
_PORTB_RB6_POSN | none | 0x6 |
_PORTB_RB6_POSITION | none | 0x6 |
_PORTB_RB6_SIZE | none | 0x1 |
_PORTB_RB6_LENGTH | none | 0x1 |
_PORTB_RB6_MASK | none | 0x40 |
_PORTB_RB7_POSN | none | 0x7 |
_PORTB_RB7_POSITION | none | 0x7 |
_PORTB_RB7_SIZE | none | 0x1 |
_PORTB_RB7_LENGTH | none | 0x1 |
_PORTB_RB7_MASK | none | 0x80 |
_PORTB_INT0_POSN | none | 0x0 |
_PORTB_INT0_POSITION | none | 0x0 |
_PORTB_INT0_SIZE | none | 0x1 |
_PORTB_INT0_LENGTH | none | 0x1 |
_PORTB_INT0_MASK | none | 0x1 |
_PORTB_INT1_POSN | none | 0x1 |
_PORTB_INT1_POSITION | none | 0x1 |
_PORTB_INT1_SIZE | none | 0x1 |
_PORTB_INT1_LENGTH | none | 0x1 |
_PORTB_INT1_MASK | none | 0x2 |
_PORTB_INT2_POSN | none | 0x2 |
_PORTB_INT2_POSITION | none | 0x2 |
_PORTB_INT2_SIZE | none | 0x1 |
_PORTB_INT2_LENGTH | none | 0x1 |
_PORTB_INT2_MASK | none | 0x4 |
_PORTB_PGM_POSN | none | 0x5 |
_PORTB_PGM_POSITION | none | 0x5 |
_PORTB_PGM_SIZE | none | 0x1 |
_PORTB_PGM_LENGTH | none | 0x1 |
_PORTB_PGM_MASK | none | 0x20 |
_PORTB_PGC_POSN | none | 0x6 |
_PORTB_PGC_POSITION | none | 0x6 |
_PORTB_PGC_SIZE | none | 0x1 |
_PORTB_PGC_LENGTH | none | 0x1 |
_PORTB_PGC_MASK | none | 0x40 |
_PORTB_PGD_POSN | none | 0x7 |
_PORTB_PGD_POSITION | none | 0x7 |
_PORTB_PGD_SIZE | none | 0x1 |
_PORTB_PGD_LENGTH | none | 0x1 |
_PORTB_PGD_MASK | none | 0x80 |
_PORTB_CCP2_PA2_POSN | none | 0x3 |
_PORTB_CCP2_PA2_POSITION | none | 0x3 |
_PORTB_CCP2_PA2_SIZE | none | 0x1 |
_PORTB_CCP2_PA2_LENGTH | none | 0x1 |
_PORTB_CCP2_PA2_MASK | none | 0x8 |
_PORTC_RC0_POSN | none | 0x0 |
_PORTC_RC0_POSITION | none | 0x0 |
_PORTC_RC0_SIZE | none | 0x1 |
_PORTC_RC0_LENGTH | none | 0x1 |
_PORTC_RC0_MASK | none | 0x1 |
_PORTC_RC1_POSN | none | 0x1 |
_PORTC_RC1_POSITION | none | 0x1 |
_PORTC_RC1_SIZE | none | 0x1 |
_PORTC_RC1_LENGTH | none | 0x1 |
_PORTC_RC1_MASK | none | 0x2 |
_PORTC_RC2_POSN | none | 0x2 |
_PORTC_RC2_POSITION | none | 0x2 |
_PORTC_RC2_SIZE | none | 0x1 |
_PORTC_RC2_LENGTH | none | 0x1 |
_PORTC_RC2_MASK | none | 0x4 |
_PORTC_RC4_POSN | none | 0x4 |
_PORTC_RC4_POSITION | none | 0x4 |
_PORTC_RC4_SIZE | none | 0x1 |
_PORTC_RC4_LENGTH | none | 0x1 |
_PORTC_RC4_MASK | none | 0x10 |
_PORTC_RC5_POSN | none | 0x5 |
_PORTC_RC5_POSITION | none | 0x5 |
_PORTC_RC5_SIZE | none | 0x1 |
_PORTC_RC5_LENGTH | none | 0x1 |
_PORTC_RC5_MASK | none | 0x20 |
_PORTC_RC6_POSN | none | 0x6 |
_PORTC_RC6_POSITION | none | 0x6 |
_PORTC_RC6_SIZE | none | 0x1 |
_PORTC_RC6_LENGTH | none | 0x1 |
_PORTC_RC6_MASK | none | 0x40 |
_PORTC_RC7_POSN | none | 0x7 |
_PORTC_RC7_POSITION | none | 0x7 |
_PORTC_RC7_SIZE | none | 0x1 |
_PORTC_RC7_LENGTH | none | 0x1 |
_PORTC_RC7_MASK | none | 0x80 |
_PORTC_T1OSO_POSN | none | 0x0 |
_PORTC_T1OSO_POSITION | none | 0x0 |
_PORTC_T1OSO_SIZE | none | 0x1 |
_PORTC_T1OSO_LENGTH | none | 0x1 |
_PORTC_T1OSO_MASK | none | 0x1 |
_PORTC_T1OSI_POSN | none | 0x1 |
_PORTC_T1OSI_POSITION | none | 0x1 |
_PORTC_T1OSI_SIZE | none | 0x1 |
_PORTC_T1OSI_LENGTH | none | 0x1 |
_PORTC_T1OSI_MASK | none | 0x2 |
_PORTC_CCP1_POSN | none | 0x2 |
_PORTC_CCP1_POSITION | none | 0x2 |
_PORTC_CCP1_SIZE | none | 0x1 |
_PORTC_CCP1_LENGTH | none | 0x1 |
_PORTC_CCP1_MASK | none | 0x4 |
_PORTC_TX_POSN | none | 0x6 |
_PORTC_TX_POSITION | none | 0x6 |
_PORTC_TX_SIZE | none | 0x1 |
_PORTC_TX_LENGTH | none | 0x1 |
_PORTC_TX_MASK | none | 0x40 |
_PORTC_RX_POSN | none | 0x7 |
_PORTC_RX_POSITION | none | 0x7 |
_PORTC_RX_SIZE | none | 0x1 |
_PORTC_RX_LENGTH | none | 0x1 |
_PORTC_RX_MASK | none | 0x80 |
_PORTC_T13CKI_POSN | none | 0x0 |
_PORTC_T13CKI_POSITION | none | 0x0 |
_PORTC_T13CKI_SIZE | none | 0x1 |
_PORTC_T13CKI_LENGTH | none | 0x1 |
_PORTC_T13CKI_MASK | none | 0x1 |
_PORTC_P1A_POSN | none | 0x2 |
_PORTC_P1A_POSITION | none | 0x2 |
_PORTC_P1A_SIZE | none | 0x1 |
_PORTC_P1A_LENGTH | none | 0x1 |
_PORTC_P1A_MASK | none | 0x4 |
_PORTC_CK_POSN | none | 0x6 |
_PORTC_CK_POSITION | none | 0x6 |
_PORTC_CK_SIZE | none | 0x1 |
_PORTC_CK_LENGTH | none | 0x1 |
_PORTC_CK_MASK | none | 0x40 |
_PORTC_DT_POSN | none | 0x7 |
_PORTC_DT_POSITION | none | 0x7 |
_PORTC_DT_SIZE | none | 0x1 |
_PORTC_DT_LENGTH | none | 0x1 |
_PORTC_DT_MASK | none | 0x80 |
_PORTC_CCP2_POSN | none | 0x1 |
_PORTC_CCP2_POSITION | none | 0x1 |
_PORTC_CCP2_SIZE | none | 0x1 |
_PORTC_CCP2_LENGTH | none | 0x1 |
_PORTC_CCP2_MASK | none | 0x2 |
_PORTC_PA1_POSN | none | 0x2 |
_PORTC_PA1_POSITION | none | 0x2 |
_PORTC_PA1_SIZE | none | 0x1 |
_PORTC_PA1_LENGTH | none | 0x1 |
_PORTC_PA1_MASK | none | 0x4 |
_PORTC_PA2_POSN | none | 0x1 |
_PORTC_PA2_POSITION | none | 0x1 |
_PORTC_PA2_SIZE | none | 0x1 |
_PORTC_PA2_LENGTH | none | 0x1 |
_PORTC_PA2_MASK | none | 0x2 |
_PORTC_RC3_POSN | none | 0x3 |
_PORTC_RC3_POSITION | none | 0x3 |
_PORTC_RC3_SIZE | none | 0x1 |
_PORTC_RC3_LENGTH | none | 0x1 |
_PORTC_RC3_MASK | none | 0x8 |
_PORTD_RD0_POSN | none | 0x0 |
_PORTD_RD0_POSITION | none | 0x0 |
_PORTD_RD0_SIZE | none | 0x1 |
_PORTD_RD0_LENGTH | none | 0x1 |
_PORTD_RD0_MASK | none | 0x1 |
_PORTD_RD1_POSN | none | 0x1 |
_PORTD_RD1_POSITION | none | 0x1 |
_PORTD_RD1_SIZE | none | 0x1 |
_PORTD_RD1_LENGTH | none | 0x1 |
_PORTD_RD1_MASK | none | 0x2 |
_PORTD_RD2_POSN | none | 0x2 |
_PORTD_RD2_POSITION | none | 0x2 |
_PORTD_RD2_SIZE | none | 0x1 |
_PORTD_RD2_LENGTH | none | 0x1 |
_PORTD_RD2_MASK | none | 0x4 |
_PORTD_RD3_POSN | none | 0x3 |
_PORTD_RD3_POSITION | none | 0x3 |
_PORTD_RD3_SIZE | none | 0x1 |
_PORTD_RD3_LENGTH | none | 0x1 |
_PORTD_RD3_MASK | none | 0x8 |
_PORTD_RD4_POSN | none | 0x4 |
_PORTD_RD4_POSITION | none | 0x4 |
_PORTD_RD4_SIZE | none | 0x1 |
_PORTD_RD4_LENGTH | none | 0x1 |
_PORTD_RD4_MASK | none | 0x10 |
_PORTD_RD5_POSN | none | 0x5 |
_PORTD_RD5_POSITION | none | 0x5 |
_PORTD_RD5_SIZE | none | 0x1 |
_PORTD_RD5_LENGTH | none | 0x1 |
_PORTD_RD5_MASK | none | 0x20 |
_PORTD_RD6_POSN | none | 0x6 |
_PORTD_RD6_POSITION | none | 0x6 |
_PORTD_RD6_SIZE | none | 0x1 |
_PORTD_RD6_LENGTH | none | 0x1 |
_PORTD_RD6_MASK | none | 0x40 |
_PORTD_RD7_POSN | none | 0x7 |
_PORTD_RD7_POSITION | none | 0x7 |
_PORTD_RD7_SIZE | none | 0x1 |
_PORTD_RD7_LENGTH | none | 0x1 |
_PORTD_RD7_MASK | none | 0x80 |
_PORTD_SPP0_POSN | none | 0x0 |
_PORTD_SPP0_POSITION | none | 0x0 |
_PORTD_SPP0_SIZE | none | 0x1 |
_PORTD_SPP0_LENGTH | none | 0x1 |
_PORTD_SPP0_MASK | none | 0x1 |
_PORTD_SPP1_POSN | none | 0x1 |
_PORTD_SPP1_POSITION | none | 0x1 |
_PORTD_SPP1_SIZE | none | 0x1 |
_PORTD_SPP1_LENGTH | none | 0x1 |
_PORTD_SPP1_MASK | none | 0x2 |
_PORTD_SPP2_POSN | none | 0x2 |
_PORTD_SPP2_POSITION | none | 0x2 |
_PORTD_SPP2_SIZE | none | 0x1 |
_PORTD_SPP2_LENGTH | none | 0x1 |
_PORTD_SPP2_MASK | none | 0x4 |
_PORTD_SPP3_POSN | none | 0x3 |
_PORTD_SPP3_POSITION | none | 0x3 |
_PORTD_SPP3_SIZE | none | 0x1 |
_PORTD_SPP3_LENGTH | none | 0x1 |
_PORTD_SPP3_MASK | none | 0x8 |
_PORTD_SPP4_POSN | none | 0x4 |
_PORTD_SPP4_POSITION | none | 0x4 |
_PORTD_SPP4_SIZE | none | 0x1 |
_PORTD_SPP4_LENGTH | none | 0x1 |
_PORTD_SPP4_MASK | none | 0x10 |
_PORTD_SPP5_POSN | none | 0x5 |
_PORTD_SPP5_POSITION | none | 0x5 |
_PORTD_SPP5_SIZE | none | 0x1 |
_PORTD_SPP5_LENGTH | none | 0x1 |
_PORTD_SPP5_MASK | none | 0x20 |
_PORTD_SPP6_POSN | none | 0x6 |
_PORTD_SPP6_POSITION | none | 0x6 |
_PORTD_SPP6_SIZE | none | 0x1 |
_PORTD_SPP6_LENGTH | none | 0x1 |
_PORTD_SPP6_MASK | none | 0x40 |
_PORTD_SPP7_POSN | none | 0x7 |
_PORTD_SPP7_POSITION | none | 0x7 |
_PORTD_SPP7_SIZE | none | 0x1 |
_PORTD_SPP7_LENGTH | none | 0x1 |
_PORTD_SPP7_MASK | none | 0x80 |
_PORTD_SS2_POSN | none | 0x7 |
_PORTD_SS2_POSITION | none | 0x7 |
_PORTD_SS2_SIZE | none | 0x1 |
_PORTD_SS2_LENGTH | none | 0x1 |
_PORTD_SS2_MASK | none | 0x80 |
_PORTE_RE0_POSN | none | 0x0 |
_PORTE_RE0_POSITION | none | 0x0 |
_PORTE_RE0_SIZE | none | 0x1 |
_PORTE_RE0_LENGTH | none | 0x1 |
_PORTE_RE0_MASK | none | 0x1 |
_PORTE_RE1_POSN | none | 0x1 |
_PORTE_RE1_POSITION | none | 0x1 |
_PORTE_RE1_SIZE | none | 0x1 |
_PORTE_RE1_LENGTH | none | 0x1 |
_PORTE_RE1_MASK | none | 0x2 |
_PORTE_RE2_POSN | none | 0x2 |
_PORTE_RE2_POSITION | none | 0x2 |
_PORTE_RE2_SIZE | none | 0x1 |
_PORTE_RE2_LENGTH | none | 0x1 |
_PORTE_RE2_MASK | none | 0x4 |
_PORTE_RE3_POSN | none | 0x3 |
_PORTE_RE3_POSITION | none | 0x3 |
_PORTE_RE3_SIZE | none | 0x1 |
_PORTE_RE3_LENGTH | none | 0x1 |
_PORTE_RE3_MASK | none | 0x8 |
_PORTE_RDPU_POSN | none | 0x7 |
_PORTE_RDPU_POSITION | none | 0x7 |
_PORTE_RDPU_SIZE | none | 0x1 |
_PORTE_RDPU_LENGTH | none | 0x1 |
_PORTE_RDPU_MASK | none | 0x80 |
_PORTE_CK1SPP_POSN | none | 0x0 |
_PORTE_CK1SPP_POSITION | none | 0x0 |
_PORTE_CK1SPP_SIZE | none | 0x1 |
_PORTE_CK1SPP_LENGTH | none | 0x1 |
_PORTE_CK1SPP_MASK | none | 0x1 |
_PORTE_CK2SPP_POSN | none | 0x1 |
_PORTE_CK2SPP_POSITION | none | 0x1 |
_PORTE_CK2SPP_SIZE | none | 0x1 |
_PORTE_CK2SPP_LENGTH | none | 0x1 |
_PORTE_CK2SPP_MASK | none | 0x2 |
_PORTE_OESPP_POSN | none | 0x2 |
_PORTE_OESPP_POSITION | none | 0x2 |
_PORTE_OESPP_SIZE | none | 0x1 |
_PORTE_OESPP_LENGTH | none | 0x1 |
_PORTE_OESPP_MASK | none | 0x4 |
_PORTE_CCP10_POSN | none | 0x2 |
_PORTE_CCP10_POSITION | none | 0x2 |
_PORTE_CCP10_SIZE | none | 0x1 |
_PORTE_CCP10_LENGTH | none | 0x1 |
_PORTE_CCP10_MASK | none | 0x4 |
_PORTE_CCP2E_POSN | none | 0x7 |
_PORTE_CCP2E_POSITION | none | 0x7 |
_PORTE_CCP2E_SIZE | none | 0x1 |
_PORTE_CCP2E_LENGTH | none | 0x1 |
_PORTE_CCP2E_MASK | none | 0x80 |
_PORTE_CCP6E_POSN | none | 0x6 |
_PORTE_CCP6E_POSITION | none | 0x6 |
_PORTE_CCP6E_SIZE | none | 0x1 |
_PORTE_CCP6E_LENGTH | none | 0x1 |
_PORTE_CCP6E_MASK | none | 0x40 |
_PORTE_CCP7E_POSN | none | 0x5 |
_PORTE_CCP7E_POSITION | none | 0x5 |
_PORTE_CCP7E_SIZE | none | 0x1 |
_PORTE_CCP7E_LENGTH | none | 0x1 |
_PORTE_CCP7E_MASK | none | 0x20 |
_PORTE_CCP8E_POSN | none | 0x4 |
_PORTE_CCP8E_POSITION | none | 0x4 |
_PORTE_CCP8E_SIZE | none | 0x1 |
_PORTE_CCP8E_LENGTH | none | 0x1 |
_PORTE_CCP8E_MASK | none | 0x10 |
_PORTE_CCP9E_POSN | none | 0x3 |
_PORTE_CCP9E_POSITION | none | 0x3 |
_PORTE_CCP9E_SIZE | none | 0x1 |
_PORTE_CCP9E_LENGTH | none | 0x1 |
_PORTE_CCP9E_MASK | none | 0x8 |
_PORTE_CS_POSN | none | 0x2 |
_PORTE_CS_POSITION | none | 0x2 |
_PORTE_CS_SIZE | none | 0x1 |
_PORTE_CS_LENGTH | none | 0x1 |
_PORTE_CS_MASK | none | 0x4 |
_PORTE_PA2E_POSN | none | 0x7 |
_PORTE_PA2E_POSITION | none | 0x7 |
_PORTE_PA2E_SIZE | none | 0x1 |
_PORTE_PA2E_LENGTH | none | 0x1 |
_PORTE_PA2E_MASK | none | 0x80 |
_PORTE_PB1E_POSN | none | 0x6 |
_PORTE_PB1E_POSITION | none | 0x6 |
_PORTE_PB1E_SIZE | none | 0x1 |
_PORTE_PB1E_LENGTH | none | 0x1 |
_PORTE_PB1E_MASK | none | 0x40 |
_PORTE_PB2_POSN | none | 0x2 |
_PORTE_PB2_POSITION | none | 0x2 |
_PORTE_PB2_SIZE | none | 0x1 |
_PORTE_PB2_LENGTH | none | 0x1 |
_PORTE_PB2_MASK | none | 0x4 |
_PORTE_PB3E_POSN | none | 0x4 |
_PORTE_PB3E_POSITION | none | 0x4 |
_PORTE_PB3E_SIZE | none | 0x1 |
_PORTE_PB3E_LENGTH | none | 0x1 |
_PORTE_PB3E_MASK | none | 0x10 |
_PORTE_PC1E_POSN | none | 0x5 |
_PORTE_PC1E_POSITION | none | 0x5 |
_PORTE_PC1E_SIZE | none | 0x1 |
_PORTE_PC1E_LENGTH | none | 0x1 |
_PORTE_PC1E_MASK | none | 0x20 |
_PORTE_PC2_POSN | none | 0x1 |
_PORTE_PC2_POSITION | none | 0x1 |
_PORTE_PC2_SIZE | none | 0x1 |
_PORTE_PC2_LENGTH | none | 0x1 |
_PORTE_PC2_MASK | none | 0x2 |
_PORTE_PC3E_POSN | none | 0x3 |
_PORTE_PC3E_POSITION | none | 0x3 |
_PORTE_PC3E_SIZE | none | 0x1 |
_PORTE_PC3E_LENGTH | none | 0x1 |
_PORTE_PC3E_MASK | none | 0x8 |
_PORTE_PD2_POSN | none | 0x0 |
_PORTE_PD2_POSITION | none | 0x0 |
_PORTE_PD2_SIZE | none | 0x1 |
_PORTE_PD2_LENGTH | none | 0x1 |
_PORTE_PD2_MASK | none | 0x1 |
_PORTE_RDE_POSN | none | 0x0 |
_PORTE_RDE_POSITION | none | 0x0 |
_PORTE_RDE_SIZE | none | 0x1 |
_PORTE_RDE_LENGTH | none | 0x1 |
_PORTE_RDE_MASK | none | 0x1 |
_PORTE_RE4_POSN | none | 0x4 |
_PORTE_RE4_POSITION | none | 0x4 |
_PORTE_RE4_SIZE | none | 0x1 |
_PORTE_RE4_LENGTH | none | 0x1 |
_PORTE_RE4_MASK | none | 0x10 |
_PORTE_RE5_POSN | none | 0x5 |
_PORTE_RE5_POSITION | none | 0x5 |
_PORTE_RE5_SIZE | none | 0x1 |
_PORTE_RE5_LENGTH | none | 0x1 |
_PORTE_RE5_MASK | none | 0x20 |
_PORTE_RE6_POSN | none | 0x6 |
_PORTE_RE6_POSITION | none | 0x6 |
_PORTE_RE6_SIZE | none | 0x1 |
_PORTE_RE6_LENGTH | none | 0x1 |
_PORTE_RE6_MASK | none | 0x40 |
_PORTE_RE7_POSN | none | 0x7 |
_PORTE_RE7_POSITION | none | 0x7 |
_PORTE_RE7_SIZE | none | 0x1 |
_PORTE_RE7_LENGTH | none | 0x1 |
_PORTE_RE7_MASK | none | 0x80 |
_PORTE_WRE_POSN | none | 0x1 |
_PORTE_WRE_POSITION | none | 0x1 |
_PORTE_WRE_SIZE | none | 0x1 |
_PORTE_WRE_LENGTH | none | 0x1 |
_PORTE_WRE_MASK | none | 0x2 |
_LATA_LATA0_POSN | none | 0x0 |
_LATA_LATA0_POSITION | none | 0x0 |
_LATA_LATA0_SIZE | none | 0x1 |
_LATA_LATA0_LENGTH | none | 0x1 |
_LATA_LATA0_MASK | none | 0x1 |
_LATA_LATA1_POSN | none | 0x1 |
_LATA_LATA1_POSITION | none | 0x1 |
_LATA_LATA1_SIZE | none | 0x1 |
_LATA_LATA1_LENGTH | none | 0x1 |
_LATA_LATA1_MASK | none | 0x2 |
_LATA_LATA2_POSN | none | 0x2 |
_LATA_LATA2_POSITION | none | 0x2 |
_LATA_LATA2_SIZE | none | 0x1 |
_LATA_LATA2_LENGTH | none | 0x1 |
_LATA_LATA2_MASK | none | 0x4 |
_LATA_LATA3_POSN | none | 0x3 |
_LATA_LATA3_POSITION | none | 0x3 |
_LATA_LATA3_SIZE | none | 0x1 |
_LATA_LATA3_LENGTH | none | 0x1 |
_LATA_LATA3_MASK | none | 0x8 |
_LATA_LATA4_POSN | none | 0x4 |
_LATA_LATA4_POSITION | none | 0x4 |
_LATA_LATA4_SIZE | none | 0x1 |
_LATA_LATA4_LENGTH | none | 0x1 |
_LATA_LATA4_MASK | none | 0x10 |
_LATA_LATA5_POSN | none | 0x5 |
_LATA_LATA5_POSITION | none | 0x5 |
_LATA_LATA5_SIZE | none | 0x1 |
_LATA_LATA5_LENGTH | none | 0x1 |
_LATA_LATA5_MASK | none | 0x20 |
_LATA_LATA6_POSN | none | 0x6 |
_LATA_LATA6_POSITION | none | 0x6 |
_LATA_LATA6_SIZE | none | 0x1 |
_LATA_LATA6_LENGTH | none | 0x1 |
_LATA_LATA6_MASK | none | 0x40 |
_LATA_LA0_POSN | none | 0x0 |
_LATA_LA0_POSITION | none | 0x0 |
_LATA_LA0_SIZE | none | 0x1 |
_LATA_LA0_LENGTH | none | 0x1 |
_LATA_LA0_MASK | none | 0x1 |
_LATA_LA1_POSN | none | 0x1 |
_LATA_LA1_POSITION | none | 0x1 |
_LATA_LA1_SIZE | none | 0x1 |
_LATA_LA1_LENGTH | none | 0x1 |
_LATA_LA1_MASK | none | 0x2 |
_LATA_LA2_POSN | none | 0x2 |
_LATA_LA2_POSITION | none | 0x2 |
_LATA_LA2_SIZE | none | 0x1 |
_LATA_LA2_LENGTH | none | 0x1 |
_LATA_LA2_MASK | none | 0x4 |
_LATA_LA3_POSN | none | 0x3 |
_LATA_LA3_POSITION | none | 0x3 |
_LATA_LA3_SIZE | none | 0x1 |
_LATA_LA3_LENGTH | none | 0x1 |
_LATA_LA3_MASK | none | 0x8 |
_LATA_LA4_POSN | none | 0x4 |
_LATA_LA4_POSITION | none | 0x4 |
_LATA_LA4_SIZE | none | 0x1 |
_LATA_LA4_LENGTH | none | 0x1 |
_LATA_LA4_MASK | none | 0x10 |
_LATA_LA5_POSN | none | 0x5 |
_LATA_LA5_POSITION | none | 0x5 |
_LATA_LA5_SIZE | none | 0x1 |
_LATA_LA5_LENGTH | none | 0x1 |
_LATA_LA5_MASK | none | 0x20 |
_LATA_LA6_POSN | none | 0x6 |
_LATA_LA6_POSITION | none | 0x6 |
_LATA_LA6_SIZE | none | 0x1 |
_LATA_LA6_LENGTH | none | 0x1 |
_LATA_LA6_MASK | none | 0x40 |
_LATA_LA7_POSN | none | 0x7 |
_LATA_LA7_POSITION | none | 0x7 |
_LATA_LA7_SIZE | none | 0x1 |
_LATA_LA7_LENGTH | none | 0x1 |
_LATA_LA7_MASK | none | 0x80 |
_LATA_LATA7_POSN | none | 0x7 |
_LATA_LATA7_POSITION | none | 0x7 |
_LATA_LATA7_SIZE | none | 0x1 |
_LATA_LATA7_LENGTH | none | 0x1 |
_LATA_LATA7_MASK | none | 0x80 |
_LATB_LATB0_POSN | none | 0x0 |
_LATB_LATB0_POSITION | none | 0x0 |
_LATB_LATB0_SIZE | none | 0x1 |
_LATB_LATB0_LENGTH | none | 0x1 |
_LATB_LATB0_MASK | none | 0x1 |
_LATB_LATB1_POSN | none | 0x1 |
_LATB_LATB1_POSITION | none | 0x1 |
_LATB_LATB1_SIZE | none | 0x1 |
_LATB_LATB1_LENGTH | none | 0x1 |
_LATB_LATB1_MASK | none | 0x2 |
_LATB_LATB2_POSN | none | 0x2 |
_LATB_LATB2_POSITION | none | 0x2 |
_LATB_LATB2_SIZE | none | 0x1 |
_LATB_LATB2_LENGTH | none | 0x1 |
_LATB_LATB2_MASK | none | 0x4 |
_LATB_LATB3_POSN | none | 0x3 |
_LATB_LATB3_POSITION | none | 0x3 |
_LATB_LATB3_SIZE | none | 0x1 |
_LATB_LATB3_LENGTH | none | 0x1 |
_LATB_LATB3_MASK | none | 0x8 |
_LATB_LATB4_POSN | none | 0x4 |
_LATB_LATB4_POSITION | none | 0x4 |
_LATB_LATB4_SIZE | none | 0x1 |
_LATB_LATB4_LENGTH | none | 0x1 |
_LATB_LATB4_MASK | none | 0x10 |
_LATB_LATB5_POSN | none | 0x5 |
_LATB_LATB5_POSITION | none | 0x5 |
_LATB_LATB5_SIZE | none | 0x1 |
_LATB_LATB5_LENGTH | none | 0x1 |
_LATB_LATB5_MASK | none | 0x20 |
_LATB_LATB6_POSN | none | 0x6 |
_LATB_LATB6_POSITION | none | 0x6 |
_LATB_LATB6_SIZE | none | 0x1 |
_LATB_LATB6_LENGTH | none | 0x1 |
_LATB_LATB6_MASK | none | 0x40 |
_LATB_LATB7_POSN | none | 0x7 |
_LATB_LATB7_POSITION | none | 0x7 |
_LATB_LATB7_SIZE | none | 0x1 |
_LATB_LATB7_LENGTH | none | 0x1 |
_LATB_LATB7_MASK | none | 0x80 |
_LATB_LB0_POSN | none | 0x0 |
_LATB_LB0_POSITION | none | 0x0 |
_LATB_LB0_SIZE | none | 0x1 |
_LATB_LB0_LENGTH | none | 0x1 |
_LATB_LB0_MASK | none | 0x1 |
_LATB_LB1_POSN | none | 0x1 |
_LATB_LB1_POSITION | none | 0x1 |
_LATB_LB1_SIZE | none | 0x1 |
_LATB_LB1_LENGTH | none | 0x1 |
_LATB_LB1_MASK | none | 0x2 |
_LATB_LB2_POSN | none | 0x2 |
_LATB_LB2_POSITION | none | 0x2 |
_LATB_LB2_SIZE | none | 0x1 |
_LATB_LB2_LENGTH | none | 0x1 |
_LATB_LB2_MASK | none | 0x4 |
_LATB_LB3_POSN | none | 0x3 |
_LATB_LB3_POSITION | none | 0x3 |
_LATB_LB3_SIZE | none | 0x1 |
_LATB_LB3_LENGTH | none | 0x1 |
_LATB_LB3_MASK | none | 0x8 |
_LATB_LB4_POSN | none | 0x4 |
_LATB_LB4_POSITION | none | 0x4 |
_LATB_LB4_SIZE | none | 0x1 |
_LATB_LB4_LENGTH | none | 0x1 |
_LATB_LB4_MASK | none | 0x10 |
_LATB_LB5_POSN | none | 0x5 |
_LATB_LB5_POSITION | none | 0x5 |
_LATB_LB5_SIZE | none | 0x1 |
_LATB_LB5_LENGTH | none | 0x1 |
_LATB_LB5_MASK | none | 0x20 |
_LATB_LB6_POSN | none | 0x6 |
_LATB_LB6_POSITION | none | 0x6 |
_LATB_LB6_SIZE | none | 0x1 |
_LATB_LB6_LENGTH | none | 0x1 |
_LATB_LB6_MASK | none | 0x40 |
_LATB_LB7_POSN | none | 0x7 |
_LATB_LB7_POSITION | none | 0x7 |
_LATB_LB7_SIZE | none | 0x1 |
_LATB_LB7_LENGTH | none | 0x1 |
_LATB_LB7_MASK | none | 0x80 |
_LATC_LATC0_POSN | none | 0x0 |
_LATC_LATC0_POSITION | none | 0x0 |
_LATC_LATC0_SIZE | none | 0x1 |
_LATC_LATC0_LENGTH | none | 0x1 |
_LATC_LATC0_MASK | none | 0x1 |
_LATC_LATC1_POSN | none | 0x1 |
_LATC_LATC1_POSITION | none | 0x1 |
_LATC_LATC1_SIZE | none | 0x1 |
_LATC_LATC1_LENGTH | none | 0x1 |
_LATC_LATC1_MASK | none | 0x2 |
_LATC_LATC2_POSN | none | 0x2 |
_LATC_LATC2_POSITION | none | 0x2 |
_LATC_LATC2_SIZE | none | 0x1 |
_LATC_LATC2_LENGTH | none | 0x1 |
_LATC_LATC2_MASK | none | 0x4 |
_LATC_LATC6_POSN | none | 0x6 |
_LATC_LATC6_POSITION | none | 0x6 |
_LATC_LATC6_SIZE | none | 0x1 |
_LATC_LATC6_LENGTH | none | 0x1 |
_LATC_LATC6_MASK | none | 0x40 |
_LATC_LATC7_POSN | none | 0x7 |
_LATC_LATC7_POSITION | none | 0x7 |
_LATC_LATC7_SIZE | none | 0x1 |
_LATC_LATC7_LENGTH | none | 0x1 |
_LATC_LATC7_MASK | none | 0x80 |
_LATC_LC0_POSN | none | 0x0 |
_LATC_LC0_POSITION | none | 0x0 |
_LATC_LC0_SIZE | none | 0x1 |
_LATC_LC0_LENGTH | none | 0x1 |
_LATC_LC0_MASK | none | 0x1 |
_LATC_LC1_POSN | none | 0x1 |
_LATC_LC1_POSITION | none | 0x1 |
_LATC_LC1_SIZE | none | 0x1 |
_LATC_LC1_LENGTH | none | 0x1 |
_LATC_LC1_MASK | none | 0x2 |
_LATC_LC2_POSN | none | 0x2 |
_LATC_LC2_POSITION | none | 0x2 |
_LATC_LC2_SIZE | none | 0x1 |
_LATC_LC2_LENGTH | none | 0x1 |
_LATC_LC2_MASK | none | 0x4 |
_LATC_LC3_POSN | none | 0x3 |
_LATC_LC3_POSITION | none | 0x3 |
_LATC_LC3_SIZE | none | 0x1 |
_LATC_LC3_LENGTH | none | 0x1 |
_LATC_LC3_MASK | none | 0x8 |
_LATC_LC4_POSN | none | 0x4 |
_LATC_LC4_POSITION | none | 0x4 |
_LATC_LC4_SIZE | none | 0x1 |
_LATC_LC4_LENGTH | none | 0x1 |
_LATC_LC4_MASK | none | 0x10 |
_LATC_LC5_POSN | none | 0x5 |
_LATC_LC5_POSITION | none | 0x5 |
_LATC_LC5_SIZE | none | 0x1 |
_LATC_LC5_LENGTH | none | 0x1 |
_LATC_LC5_MASK | none | 0x20 |
_LATC_LC6_POSN | none | 0x6 |
_LATC_LC6_POSITION | none | 0x6 |
_LATC_LC6_SIZE | none | 0x1 |
_LATC_LC6_LENGTH | none | 0x1 |
_LATC_LC6_MASK | none | 0x40 |
_LATC_LC7_POSN | none | 0x7 |
_LATC_LC7_POSITION | none | 0x7 |
_LATC_LC7_SIZE | none | 0x1 |
_LATC_LC7_LENGTH | none | 0x1 |
_LATC_LC7_MASK | none | 0x80 |
_LATD_LATD0_POSN | none | 0x0 |
_LATD_LATD0_POSITION | none | 0x0 |
_LATD_LATD0_SIZE | none | 0x1 |
_LATD_LATD0_LENGTH | none | 0x1 |
_LATD_LATD0_MASK | none | 0x1 |
_LATD_LATD1_POSN | none | 0x1 |
_LATD_LATD1_POSITION | none | 0x1 |
_LATD_LATD1_SIZE | none | 0x1 |
_LATD_LATD1_LENGTH | none | 0x1 |
_LATD_LATD1_MASK | none | 0x2 |
_LATD_LATD2_POSN | none | 0x2 |
_LATD_LATD2_POSITION | none | 0x2 |
_LATD_LATD2_SIZE | none | 0x1 |
_LATD_LATD2_LENGTH | none | 0x1 |
_LATD_LATD2_MASK | none | 0x4 |
_LATD_LATD3_POSN | none | 0x3 |
_LATD_LATD3_POSITION | none | 0x3 |
_LATD_LATD3_SIZE | none | 0x1 |
_LATD_LATD3_LENGTH | none | 0x1 |
_LATD_LATD3_MASK | none | 0x8 |
_LATD_LATD4_POSN | none | 0x4 |
_LATD_LATD4_POSITION | none | 0x4 |
_LATD_LATD4_SIZE | none | 0x1 |
_LATD_LATD4_LENGTH | none | 0x1 |
_LATD_LATD4_MASK | none | 0x10 |
_LATD_LATD5_POSN | none | 0x5 |
_LATD_LATD5_POSITION | none | 0x5 |
_LATD_LATD5_SIZE | none | 0x1 |
_LATD_LATD5_LENGTH | none | 0x1 |
_LATD_LATD5_MASK | none | 0x20 |
_LATD_LATD6_POSN | none | 0x6 |
_LATD_LATD6_POSITION | none | 0x6 |
_LATD_LATD6_SIZE | none | 0x1 |
_LATD_LATD6_LENGTH | none | 0x1 |
_LATD_LATD6_MASK | none | 0x40 |
_LATD_LATD7_POSN | none | 0x7 |
_LATD_LATD7_POSITION | none | 0x7 |
_LATD_LATD7_SIZE | none | 0x1 |
_LATD_LATD7_LENGTH | none | 0x1 |
_LATD_LATD7_MASK | none | 0x80 |
_LATD_LD0_POSN | none | 0x0 |
_LATD_LD0_POSITION | none | 0x0 |
_LATD_LD0_SIZE | none | 0x1 |
_LATD_LD0_LENGTH | none | 0x1 |
_LATD_LD0_MASK | none | 0x1 |
_LATD_LD1_POSN | none | 0x1 |
_LATD_LD1_POSITION | none | 0x1 |
_LATD_LD1_SIZE | none | 0x1 |
_LATD_LD1_LENGTH | none | 0x1 |
_LATD_LD1_MASK | none | 0x2 |
_LATD_LD2_POSN | none | 0x2 |
_LATD_LD2_POSITION | none | 0x2 |
_LATD_LD2_SIZE | none | 0x1 |
_LATD_LD2_LENGTH | none | 0x1 |
_LATD_LD2_MASK | none | 0x4 |
_LATD_LD3_POSN | none | 0x3 |
_LATD_LD3_POSITION | none | 0x3 |
_LATD_LD3_SIZE | none | 0x1 |
_LATD_LD3_LENGTH | none | 0x1 |
_LATD_LD3_MASK | none | 0x8 |
_LATD_LD4_POSN | none | 0x4 |
_LATD_LD4_POSITION | none | 0x4 |
_LATD_LD4_SIZE | none | 0x1 |
_LATD_LD4_LENGTH | none | 0x1 |
_LATD_LD4_MASK | none | 0x10 |
_LATD_LD5_POSN | none | 0x5 |
_LATD_LD5_POSITION | none | 0x5 |
_LATD_LD5_SIZE | none | 0x1 |
_LATD_LD5_LENGTH | none | 0x1 |
_LATD_LD5_MASK | none | 0x20 |
_LATD_LD6_POSN | none | 0x6 |
_LATD_LD6_POSITION | none | 0x6 |
_LATD_LD6_SIZE | none | 0x1 |
_LATD_LD6_LENGTH | none | 0x1 |
_LATD_LD6_MASK | none | 0x40 |
_LATD_LD7_POSN | none | 0x7 |
_LATD_LD7_POSITION | none | 0x7 |
_LATD_LD7_SIZE | none | 0x1 |
_LATD_LD7_LENGTH | none | 0x1 |
_LATD_LD7_MASK | none | 0x80 |
_LATE_LATE0_POSN | none | 0x0 |
_LATE_LATE0_POSITION | none | 0x0 |
_LATE_LATE0_SIZE | none | 0x1 |
_LATE_LATE0_LENGTH | none | 0x1 |
_LATE_LATE0_MASK | none | 0x1 |
_LATE_LATE1_POSN | none | 0x1 |
_LATE_LATE1_POSITION | none | 0x1 |
_LATE_LATE1_SIZE | none | 0x1 |
_LATE_LATE1_LENGTH | none | 0x1 |
_LATE_LATE1_MASK | none | 0x2 |
_LATE_LATE2_POSN | none | 0x2 |
_LATE_LATE2_POSITION | none | 0x2 |
_LATE_LATE2_SIZE | none | 0x1 |
_LATE_LATE2_LENGTH | none | 0x1 |
_LATE_LATE2_MASK | none | 0x4 |
_LATE_LE0_POSN | none | 0x0 |
_LATE_LE0_POSITION | none | 0x0 |
_LATE_LE0_SIZE | none | 0x1 |
_LATE_LE0_LENGTH | none | 0x1 |
_LATE_LE0_MASK | none | 0x1 |
_LATE_LE1_POSN | none | 0x1 |
_LATE_LE1_POSITION | none | 0x1 |
_LATE_LE1_SIZE | none | 0x1 |
_LATE_LE1_LENGTH | none | 0x1 |
_LATE_LE1_MASK | none | 0x2 |
_LATE_LE2_POSN | none | 0x2 |
_LATE_LE2_POSITION | none | 0x2 |
_LATE_LE2_SIZE | none | 0x1 |
_LATE_LE2_LENGTH | none | 0x1 |
_LATE_LE2_MASK | none | 0x4 |
_LATE_LE3_POSN | none | 0x3 |
_LATE_LE3_POSITION | none | 0x3 |
_LATE_LE3_SIZE | none | 0x1 |
_LATE_LE3_LENGTH | none | 0x1 |
_LATE_LE3_MASK | none | 0x8 |
_LATE_LE4_POSN | none | 0x4 |
_LATE_LE4_POSITION | none | 0x4 |
_LATE_LE4_SIZE | none | 0x1 |
_LATE_LE4_LENGTH | none | 0x1 |
_LATE_LE4_MASK | none | 0x10 |
_LATE_LE5_POSN | none | 0x5 |
_LATE_LE5_POSITION | none | 0x5 |
_LATE_LE5_SIZE | none | 0x1 |
_LATE_LE5_LENGTH | none | 0x1 |
_LATE_LE5_MASK | none | 0x20 |
_LATE_LE6_POSN | none | 0x6 |
_LATE_LE6_POSITION | none | 0x6 |
_LATE_LE6_SIZE | none | 0x1 |
_LATE_LE6_LENGTH | none | 0x1 |
_LATE_LE6_MASK | none | 0x40 |
_LATE_LE7_POSN | none | 0x7 |
_LATE_LE7_POSITION | none | 0x7 |
_LATE_LE7_SIZE | none | 0x1 |
_LATE_LE7_LENGTH | none | 0x1 |
_LATE_LE7_MASK | none | 0x80 |
_TRISA_TRISA0_POSN | none | 0x0 |
_TRISA_TRISA0_POSITION | none | 0x0 |
_TRISA_TRISA0_SIZE | none | 0x1 |
_TRISA_TRISA0_LENGTH | none | 0x1 |
_TRISA_TRISA0_MASK | none | 0x1 |
_TRISA_TRISA1_POSN | none | 0x1 |
_TRISA_TRISA1_POSITION | none | 0x1 |
_TRISA_TRISA1_SIZE | none | 0x1 |
_TRISA_TRISA1_LENGTH | none | 0x1 |
_TRISA_TRISA1_MASK | none | 0x2 |
_TRISA_TRISA2_POSN | none | 0x2 |
_TRISA_TRISA2_POSITION | none | 0x2 |
_TRISA_TRISA2_SIZE | none | 0x1 |
_TRISA_TRISA2_LENGTH | none | 0x1 |
_TRISA_TRISA2_MASK | none | 0x4 |
_TRISA_TRISA3_POSN | none | 0x3 |
_TRISA_TRISA3_POSITION | none | 0x3 |
_TRISA_TRISA3_SIZE | none | 0x1 |
_TRISA_TRISA3_LENGTH | none | 0x1 |
_TRISA_TRISA3_MASK | none | 0x8 |
_TRISA_TRISA4_POSN | none | 0x4 |
_TRISA_TRISA4_POSITION | none | 0x4 |
_TRISA_TRISA4_SIZE | none | 0x1 |
_TRISA_TRISA4_LENGTH | none | 0x1 |
_TRISA_TRISA4_MASK | none | 0x10 |
_TRISA_TRISA5_POSN | none | 0x5 |
_TRISA_TRISA5_POSITION | none | 0x5 |
_TRISA_TRISA5_SIZE | none | 0x1 |
_TRISA_TRISA5_LENGTH | none | 0x1 |
_TRISA_TRISA5_MASK | none | 0x20 |
_TRISA_TRISA6_POSN | none | 0x6 |
_TRISA_TRISA6_POSITION | none | 0x6 |
_TRISA_TRISA6_SIZE | none | 0x1 |
_TRISA_TRISA6_LENGTH | none | 0x1 |
_TRISA_TRISA6_MASK | none | 0x40 |
_TRISA_RA0_POSN | none | 0x0 |
_TRISA_RA0_POSITION | none | 0x0 |
_TRISA_RA0_SIZE | none | 0x1 |
_TRISA_RA0_LENGTH | none | 0x1 |
_TRISA_RA0_MASK | none | 0x1 |
_TRISA_RA1_POSN | none | 0x1 |
_TRISA_RA1_POSITION | none | 0x1 |
_TRISA_RA1_SIZE | none | 0x1 |
_TRISA_RA1_LENGTH | none | 0x1 |
_TRISA_RA1_MASK | none | 0x2 |
_TRISA_RA2_POSN | none | 0x2 |
_TRISA_RA2_POSITION | none | 0x2 |
_TRISA_RA2_SIZE | none | 0x1 |
_TRISA_RA2_LENGTH | none | 0x1 |
_TRISA_RA2_MASK | none | 0x4 |
_TRISA_RA3_POSN | none | 0x3 |
_TRISA_RA3_POSITION | none | 0x3 |
_TRISA_RA3_SIZE | none | 0x1 |
_TRISA_RA3_LENGTH | none | 0x1 |
_TRISA_RA3_MASK | none | 0x8 |
_TRISA_RA4_POSN | none | 0x4 |
_TRISA_RA4_POSITION | none | 0x4 |
_TRISA_RA4_SIZE | none | 0x1 |
_TRISA_RA4_LENGTH | none | 0x1 |
_TRISA_RA4_MASK | none | 0x10 |
_TRISA_RA5_POSN | none | 0x5 |
_TRISA_RA5_POSITION | none | 0x5 |
_TRISA_RA5_SIZE | none | 0x1 |
_TRISA_RA5_LENGTH | none | 0x1 |
_TRISA_RA5_MASK | none | 0x20 |
_TRISA_RA6_POSN | none | 0x6 |
_TRISA_RA6_POSITION | none | 0x6 |
_TRISA_RA6_SIZE | none | 0x1 |
_TRISA_RA6_LENGTH | none | 0x1 |
_TRISA_RA6_MASK | none | 0x40 |
_DDRA_TRISA0_POSN | none | 0x0 |
_DDRA_TRISA0_POSITION | none | 0x0 |
_DDRA_TRISA0_SIZE | none | 0x1 |
_DDRA_TRISA0_LENGTH | none | 0x1 |
_DDRA_TRISA0_MASK | none | 0x1 |
_DDRA_TRISA1_POSN | none | 0x1 |
_DDRA_TRISA1_POSITION | none | 0x1 |
_DDRA_TRISA1_SIZE | none | 0x1 |
_DDRA_TRISA1_LENGTH | none | 0x1 |
_DDRA_TRISA1_MASK | none | 0x2 |
_DDRA_TRISA2_POSN | none | 0x2 |
_DDRA_TRISA2_POSITION | none | 0x2 |
_DDRA_TRISA2_SIZE | none | 0x1 |
_DDRA_TRISA2_LENGTH | none | 0x1 |
_DDRA_TRISA2_MASK | none | 0x4 |
_DDRA_TRISA3_POSN | none | 0x3 |
_DDRA_TRISA3_POSITION | none | 0x3 |
_DDRA_TRISA3_SIZE | none | 0x1 |
_DDRA_TRISA3_LENGTH | none | 0x1 |
_DDRA_TRISA3_MASK | none | 0x8 |
_DDRA_TRISA4_POSN | none | 0x4 |
_DDRA_TRISA4_POSITION | none | 0x4 |
_DDRA_TRISA4_SIZE | none | 0x1 |
_DDRA_TRISA4_LENGTH | none | 0x1 |
_DDRA_TRISA4_MASK | none | 0x10 |
_DDRA_TRISA5_POSN | none | 0x5 |
_DDRA_TRISA5_POSITION | none | 0x5 |
_DDRA_TRISA5_SIZE | none | 0x1 |
_DDRA_TRISA5_LENGTH | none | 0x1 |
_DDRA_TRISA5_MASK | none | 0x20 |
_DDRA_TRISA6_POSN | none | 0x6 |
_DDRA_TRISA6_POSITION | none | 0x6 |
_DDRA_TRISA6_SIZE | none | 0x1 |
_DDRA_TRISA6_LENGTH | none | 0x1 |
_DDRA_TRISA6_MASK | none | 0x40 |
_DDRA_RA0_POSN | none | 0x0 |
_DDRA_RA0_POSITION | none | 0x0 |
_DDRA_RA0_SIZE | none | 0x1 |
_DDRA_RA0_LENGTH | none | 0x1 |
_DDRA_RA0_MASK | none | 0x1 |
_DDRA_RA1_POSN | none | 0x1 |
_DDRA_RA1_POSITION | none | 0x1 |
_DDRA_RA1_SIZE | none | 0x1 |
_DDRA_RA1_LENGTH | none | 0x1 |
_DDRA_RA1_MASK | none | 0x2 |
_DDRA_RA2_POSN | none | 0x2 |
_DDRA_RA2_POSITION | none | 0x2 |
_DDRA_RA2_SIZE | none | 0x1 |
_DDRA_RA2_LENGTH | none | 0x1 |
_DDRA_RA2_MASK | none | 0x4 |
_DDRA_RA3_POSN | none | 0x3 |
_DDRA_RA3_POSITION | none | 0x3 |
_DDRA_RA3_SIZE | none | 0x1 |
_DDRA_RA3_LENGTH | none | 0x1 |
_DDRA_RA3_MASK | none | 0x8 |
_DDRA_RA4_POSN | none | 0x4 |
_DDRA_RA4_POSITION | none | 0x4 |
_DDRA_RA4_SIZE | none | 0x1 |
_DDRA_RA4_LENGTH | none | 0x1 |
_DDRA_RA4_MASK | none | 0x10 |
_DDRA_RA5_POSN | none | 0x5 |
_DDRA_RA5_POSITION | none | 0x5 |
_DDRA_RA5_SIZE | none | 0x1 |
_DDRA_RA5_LENGTH | none | 0x1 |
_DDRA_RA5_MASK | none | 0x20 |
_DDRA_RA6_POSN | none | 0x6 |
_DDRA_RA6_POSITION | none | 0x6 |
_DDRA_RA6_SIZE | none | 0x1 |
_DDRA_RA6_LENGTH | none | 0x1 |
_DDRA_RA6_MASK | none | 0x40 |
_TRISB_TRISB0_POSN | none | 0x0 |
_TRISB_TRISB0_POSITION | none | 0x0 |
_TRISB_TRISB0_SIZE | none | 0x1 |
_TRISB_TRISB0_LENGTH | none | 0x1 |
_TRISB_TRISB0_MASK | none | 0x1 |
_TRISB_TRISB1_POSN | none | 0x1 |
_TRISB_TRISB1_POSITION | none | 0x1 |
_TRISB_TRISB1_SIZE | none | 0x1 |
_TRISB_TRISB1_LENGTH | none | 0x1 |
_TRISB_TRISB1_MASK | none | 0x2 |
_TRISB_TRISB2_POSN | none | 0x2 |
_TRISB_TRISB2_POSITION | none | 0x2 |
_TRISB_TRISB2_SIZE | none | 0x1 |
_TRISB_TRISB2_LENGTH | none | 0x1 |
_TRISB_TRISB2_MASK | none | 0x4 |
_TRISB_TRISB3_POSN | none | 0x3 |
_TRISB_TRISB3_POSITION | none | 0x3 |
_TRISB_TRISB3_SIZE | none | 0x1 |
_TRISB_TRISB3_LENGTH | none | 0x1 |
_TRISB_TRISB3_MASK | none | 0x8 |
_TRISB_TRISB4_POSN | none | 0x4 |
_TRISB_TRISB4_POSITION | none | 0x4 |
_TRISB_TRISB4_SIZE | none | 0x1 |
_TRISB_TRISB4_LENGTH | none | 0x1 |
_TRISB_TRISB4_MASK | none | 0x10 |
_TRISB_TRISB5_POSN | none | 0x5 |
_TRISB_TRISB5_POSITION | none | 0x5 |
_TRISB_TRISB5_SIZE | none | 0x1 |
_TRISB_TRISB5_LENGTH | none | 0x1 |
_TRISB_TRISB5_MASK | none | 0x20 |
_TRISB_TRISB6_POSN | none | 0x6 |
_TRISB_TRISB6_POSITION | none | 0x6 |
_TRISB_TRISB6_SIZE | none | 0x1 |
_TRISB_TRISB6_LENGTH | none | 0x1 |
_TRISB_TRISB6_MASK | none | 0x40 |
_TRISB_TRISB7_POSN | none | 0x7 |
_TRISB_TRISB7_POSITION | none | 0x7 |
_TRISB_TRISB7_SIZE | none | 0x1 |
_TRISB_TRISB7_LENGTH | none | 0x1 |
_TRISB_TRISB7_MASK | none | 0x80 |
_TRISB_RB0_POSN | none | 0x0 |
_TRISB_RB0_POSITION | none | 0x0 |
_TRISB_RB0_SIZE | none | 0x1 |
_TRISB_RB0_LENGTH | none | 0x1 |
_TRISB_RB0_MASK | none | 0x1 |
_TRISB_RB1_POSN | none | 0x1 |
_TRISB_RB1_POSITION | none | 0x1 |
_TRISB_RB1_SIZE | none | 0x1 |
_TRISB_RB1_LENGTH | none | 0x1 |
_TRISB_RB1_MASK | none | 0x2 |
_TRISB_RB2_POSN | none | 0x2 |
_TRISB_RB2_POSITION | none | 0x2 |
_TRISB_RB2_SIZE | none | 0x1 |
_TRISB_RB2_LENGTH | none | 0x1 |
_TRISB_RB2_MASK | none | 0x4 |
_TRISB_RB3_POSN | none | 0x3 |
_TRISB_RB3_POSITION | none | 0x3 |
_TRISB_RB3_SIZE | none | 0x1 |
_TRISB_RB3_LENGTH | none | 0x1 |
_TRISB_RB3_MASK | none | 0x8 |
_TRISB_RB4_POSN | none | 0x4 |
_TRISB_RB4_POSITION | none | 0x4 |
_TRISB_RB4_SIZE | none | 0x1 |
_TRISB_RB4_LENGTH | none | 0x1 |
_TRISB_RB4_MASK | none | 0x10 |
_TRISB_RB5_POSN | none | 0x5 |
_TRISB_RB5_POSITION | none | 0x5 |
_TRISB_RB5_SIZE | none | 0x1 |
_TRISB_RB5_LENGTH | none | 0x1 |
_TRISB_RB5_MASK | none | 0x20 |
_TRISB_RB6_POSN | none | 0x6 |
_TRISB_RB6_POSITION | none | 0x6 |
_TRISB_RB6_SIZE | none | 0x1 |
_TRISB_RB6_LENGTH | none | 0x1 |
_TRISB_RB6_MASK | none | 0x40 |
_TRISB_RB7_POSN | none | 0x7 |
_TRISB_RB7_POSITION | none | 0x7 |
_TRISB_RB7_SIZE | none | 0x1 |
_TRISB_RB7_LENGTH | none | 0x1 |
_TRISB_RB7_MASK | none | 0x80 |
_DDRB_TRISB0_POSN | none | 0x0 |
_DDRB_TRISB0_POSITION | none | 0x0 |
_DDRB_TRISB0_SIZE | none | 0x1 |
_DDRB_TRISB0_LENGTH | none | 0x1 |
_DDRB_TRISB0_MASK | none | 0x1 |
_DDRB_TRISB1_POSN | none | 0x1 |
_DDRB_TRISB1_POSITION | none | 0x1 |
_DDRB_TRISB1_SIZE | none | 0x1 |
_DDRB_TRISB1_LENGTH | none | 0x1 |
_DDRB_TRISB1_MASK | none | 0x2 |
_DDRB_TRISB2_POSN | none | 0x2 |
_DDRB_TRISB2_POSITION | none | 0x2 |
_DDRB_TRISB2_SIZE | none | 0x1 |
_DDRB_TRISB2_LENGTH | none | 0x1 |
_DDRB_TRISB2_MASK | none | 0x4 |
_DDRB_TRISB3_POSN | none | 0x3 |
_DDRB_TRISB3_POSITION | none | 0x3 |
_DDRB_TRISB3_SIZE | none | 0x1 |
_DDRB_TRISB3_LENGTH | none | 0x1 |
_DDRB_TRISB3_MASK | none | 0x8 |
_DDRB_TRISB4_POSN | none | 0x4 |
_DDRB_TRISB4_POSITION | none | 0x4 |
_DDRB_TRISB4_SIZE | none | 0x1 |
_DDRB_TRISB4_LENGTH | none | 0x1 |
_DDRB_TRISB4_MASK | none | 0x10 |
_DDRB_TRISB5_POSN | none | 0x5 |
_DDRB_TRISB5_POSITION | none | 0x5 |
_DDRB_TRISB5_SIZE | none | 0x1 |
_DDRB_TRISB5_LENGTH | none | 0x1 |
_DDRB_TRISB5_MASK | none | 0x20 |
_DDRB_TRISB6_POSN | none | 0x6 |
_DDRB_TRISB6_POSITION | none | 0x6 |
_DDRB_TRISB6_SIZE | none | 0x1 |
_DDRB_TRISB6_LENGTH | none | 0x1 |
_DDRB_TRISB6_MASK | none | 0x40 |
_DDRB_TRISB7_POSN | none | 0x7 |
_DDRB_TRISB7_POSITION | none | 0x7 |
_DDRB_TRISB7_SIZE | none | 0x1 |
_DDRB_TRISB7_LENGTH | none | 0x1 |
_DDRB_TRISB7_MASK | none | 0x80 |
_DDRB_RB0_POSN | none | 0x0 |
_DDRB_RB0_POSITION | none | 0x0 |
_DDRB_RB0_SIZE | none | 0x1 |
_DDRB_RB0_LENGTH | none | 0x1 |
_DDRB_RB0_MASK | none | 0x1 |
_DDRB_RB1_POSN | none | 0x1 |
_DDRB_RB1_POSITION | none | 0x1 |
_DDRB_RB1_SIZE | none | 0x1 |
_DDRB_RB1_LENGTH | none | 0x1 |
_DDRB_RB1_MASK | none | 0x2 |
_DDRB_RB2_POSN | none | 0x2 |
_DDRB_RB2_POSITION | none | 0x2 |
_DDRB_RB2_SIZE | none | 0x1 |
_DDRB_RB2_LENGTH | none | 0x1 |
_DDRB_RB2_MASK | none | 0x4 |
_DDRB_RB3_POSN | none | 0x3 |
_DDRB_RB3_POSITION | none | 0x3 |
_DDRB_RB3_SIZE | none | 0x1 |
_DDRB_RB3_LENGTH | none | 0x1 |
_DDRB_RB3_MASK | none | 0x8 |
_DDRB_RB4_POSN | none | 0x4 |
_DDRB_RB4_POSITION | none | 0x4 |
_DDRB_RB4_SIZE | none | 0x1 |
_DDRB_RB4_LENGTH | none | 0x1 |
_DDRB_RB4_MASK | none | 0x10 |
_DDRB_RB5_POSN | none | 0x5 |
_DDRB_RB5_POSITION | none | 0x5 |
_DDRB_RB5_SIZE | none | 0x1 |
_DDRB_RB5_LENGTH | none | 0x1 |
_DDRB_RB5_MASK | none | 0x20 |
_DDRB_RB6_POSN | none | 0x6 |
_DDRB_RB6_POSITION | none | 0x6 |
_DDRB_RB6_SIZE | none | 0x1 |
_DDRB_RB6_LENGTH | none | 0x1 |
_DDRB_RB6_MASK | none | 0x40 |
_DDRB_RB7_POSN | none | 0x7 |
_DDRB_RB7_POSITION | none | 0x7 |
_DDRB_RB7_SIZE | none | 0x1 |
_DDRB_RB7_LENGTH | none | 0x1 |
_DDRB_RB7_MASK | none | 0x80 |
_TRISC_TRISC0_POSN | none | 0x0 |
_TRISC_TRISC0_POSITION | none | 0x0 |
_TRISC_TRISC0_SIZE | none | 0x1 |
_TRISC_TRISC0_LENGTH | none | 0x1 |
_TRISC_TRISC0_MASK | none | 0x1 |
_TRISC_TRISC1_POSN | none | 0x1 |
_TRISC_TRISC1_POSITION | none | 0x1 |
_TRISC_TRISC1_SIZE | none | 0x1 |
_TRISC_TRISC1_LENGTH | none | 0x1 |
_TRISC_TRISC1_MASK | none | 0x2 |
_TRISC_TRISC2_POSN | none | 0x2 |
_TRISC_TRISC2_POSITION | none | 0x2 |
_TRISC_TRISC2_SIZE | none | 0x1 |
_TRISC_TRISC2_LENGTH | none | 0x1 |
_TRISC_TRISC2_MASK | none | 0x4 |
_TRISC_TRISC6_POSN | none | 0x6 |
_TRISC_TRISC6_POSITION | none | 0x6 |
_TRISC_TRISC6_SIZE | none | 0x1 |
_TRISC_TRISC6_LENGTH | none | 0x1 |
_TRISC_TRISC6_MASK | none | 0x40 |
_TRISC_TRISC7_POSN | none | 0x7 |
_TRISC_TRISC7_POSITION | none | 0x7 |
_TRISC_TRISC7_SIZE | none | 0x1 |
_TRISC_TRISC7_LENGTH | none | 0x1 |
_TRISC_TRISC7_MASK | none | 0x80 |
_TRISC_RC0_POSN | none | 0x0 |
_TRISC_RC0_POSITION | none | 0x0 |
_TRISC_RC0_SIZE | none | 0x1 |
_TRISC_RC0_LENGTH | none | 0x1 |
_TRISC_RC0_MASK | none | 0x1 |
_TRISC_RC1_POSN | none | 0x1 |
_TRISC_RC1_POSITION | none | 0x1 |
_TRISC_RC1_SIZE | none | 0x1 |
_TRISC_RC1_LENGTH | none | 0x1 |
_TRISC_RC1_MASK | none | 0x2 |
_TRISC_RC2_POSN | none | 0x2 |
_TRISC_RC2_POSITION | none | 0x2 |
_TRISC_RC2_SIZE | none | 0x1 |
_TRISC_RC2_LENGTH | none | 0x1 |
_TRISC_RC2_MASK | none | 0x4 |
_TRISC_RC6_POSN | none | 0x6 |
_TRISC_RC6_POSITION | none | 0x6 |
_TRISC_RC6_SIZE | none | 0x1 |
_TRISC_RC6_LENGTH | none | 0x1 |
_TRISC_RC6_MASK | none | 0x40 |
_TRISC_RC7_POSN | none | 0x7 |
_TRISC_RC7_POSITION | none | 0x7 |
_TRISC_RC7_SIZE | none | 0x1 |
_TRISC_RC7_LENGTH | none | 0x1 |
_TRISC_RC7_MASK | none | 0x80 |
_TRISC_TRISC3_POSN | none | 0x3 |
_TRISC_TRISC3_POSITION | none | 0x3 |
_TRISC_TRISC3_SIZE | none | 0x1 |
_TRISC_TRISC3_LENGTH | none | 0x1 |
_TRISC_TRISC3_MASK | none | 0x8 |
_DDRC_TRISC0_POSN | none | 0x0 |
_DDRC_TRISC0_POSITION | none | 0x0 |
_DDRC_TRISC0_SIZE | none | 0x1 |
_DDRC_TRISC0_LENGTH | none | 0x1 |
_DDRC_TRISC0_MASK | none | 0x1 |
_DDRC_TRISC1_POSN | none | 0x1 |
_DDRC_TRISC1_POSITION | none | 0x1 |
_DDRC_TRISC1_SIZE | none | 0x1 |
_DDRC_TRISC1_LENGTH | none | 0x1 |
_DDRC_TRISC1_MASK | none | 0x2 |
_DDRC_TRISC2_POSN | none | 0x2 |
_DDRC_TRISC2_POSITION | none | 0x2 |
_DDRC_TRISC2_SIZE | none | 0x1 |
_DDRC_TRISC2_LENGTH | none | 0x1 |
_DDRC_TRISC2_MASK | none | 0x4 |
_DDRC_TRISC6_POSN | none | 0x6 |
_DDRC_TRISC6_POSITION | none | 0x6 |
_DDRC_TRISC6_SIZE | none | 0x1 |
_DDRC_TRISC6_LENGTH | none | 0x1 |
_DDRC_TRISC6_MASK | none | 0x40 |
_DDRC_TRISC7_POSN | none | 0x7 |
_DDRC_TRISC7_POSITION | none | 0x7 |
_DDRC_TRISC7_SIZE | none | 0x1 |
_DDRC_TRISC7_LENGTH | none | 0x1 |
_DDRC_TRISC7_MASK | none | 0x80 |
_DDRC_RC0_POSN | none | 0x0 |
_DDRC_RC0_POSITION | none | 0x0 |
_DDRC_RC0_SIZE | none | 0x1 |
_DDRC_RC0_LENGTH | none | 0x1 |
_DDRC_RC0_MASK | none | 0x1 |
_DDRC_RC1_POSN | none | 0x1 |
_DDRC_RC1_POSITION | none | 0x1 |
_DDRC_RC1_SIZE | none | 0x1 |
_DDRC_RC1_LENGTH | none | 0x1 |
_DDRC_RC1_MASK | none | 0x2 |
_DDRC_RC2_POSN | none | 0x2 |
_DDRC_RC2_POSITION | none | 0x2 |
_DDRC_RC2_SIZE | none | 0x1 |
_DDRC_RC2_LENGTH | none | 0x1 |
_DDRC_RC2_MASK | none | 0x4 |
_DDRC_RC6_POSN | none | 0x6 |
_DDRC_RC6_POSITION | none | 0x6 |
_DDRC_RC6_SIZE | none | 0x1 |
_DDRC_RC6_LENGTH | none | 0x1 |
_DDRC_RC6_MASK | none | 0x40 |
_DDRC_RC7_POSN | none | 0x7 |
_DDRC_RC7_POSITION | none | 0x7 |
_DDRC_RC7_SIZE | none | 0x1 |
_DDRC_RC7_LENGTH | none | 0x1 |
_DDRC_RC7_MASK | none | 0x80 |
_DDRC_TRISC3_POSN | none | 0x3 |
_DDRC_TRISC3_POSITION | none | 0x3 |
_DDRC_TRISC3_SIZE | none | 0x1 |
_DDRC_TRISC3_LENGTH | none | 0x1 |
_DDRC_TRISC3_MASK | none | 0x8 |
_TRISD_TRISD0_POSN | none | 0x0 |
_TRISD_TRISD0_POSITION | none | 0x0 |
_TRISD_TRISD0_SIZE | none | 0x1 |
_TRISD_TRISD0_LENGTH | none | 0x1 |
_TRISD_TRISD0_MASK | none | 0x1 |
_TRISD_TRISD1_POSN | none | 0x1 |
_TRISD_TRISD1_POSITION | none | 0x1 |
_TRISD_TRISD1_SIZE | none | 0x1 |
_TRISD_TRISD1_LENGTH | none | 0x1 |
_TRISD_TRISD1_MASK | none | 0x2 |
_TRISD_TRISD2_POSN | none | 0x2 |
_TRISD_TRISD2_POSITION | none | 0x2 |
_TRISD_TRISD2_SIZE | none | 0x1 |
_TRISD_TRISD2_LENGTH | none | 0x1 |
_TRISD_TRISD2_MASK | none | 0x4 |
_TRISD_TRISD3_POSN | none | 0x3 |
_TRISD_TRISD3_POSITION | none | 0x3 |
_TRISD_TRISD3_SIZE | none | 0x1 |
_TRISD_TRISD3_LENGTH | none | 0x1 |
_TRISD_TRISD3_MASK | none | 0x8 |
_TRISD_TRISD4_POSN | none | 0x4 |
_TRISD_TRISD4_POSITION | none | 0x4 |
_TRISD_TRISD4_SIZE | none | 0x1 |
_TRISD_TRISD4_LENGTH | none | 0x1 |
_TRISD_TRISD4_MASK | none | 0x10 |
_TRISD_TRISD5_POSN | none | 0x5 |
_TRISD_TRISD5_POSITION | none | 0x5 |
_TRISD_TRISD5_SIZE | none | 0x1 |
_TRISD_TRISD5_LENGTH | none | 0x1 |
_TRISD_TRISD5_MASK | none | 0x20 |
_TRISD_TRISD6_POSN | none | 0x6 |
_TRISD_TRISD6_POSITION | none | 0x6 |
_TRISD_TRISD6_SIZE | none | 0x1 |
_TRISD_TRISD6_LENGTH | none | 0x1 |
_TRISD_TRISD6_MASK | none | 0x40 |
_TRISD_TRISD7_POSN | none | 0x7 |
_TRISD_TRISD7_POSITION | none | 0x7 |
_TRISD_TRISD7_SIZE | none | 0x1 |
_TRISD_TRISD7_LENGTH | none | 0x1 |
_TRISD_TRISD7_MASK | none | 0x80 |
_TRISD_RD0_POSN | none | 0x0 |
_TRISD_RD0_POSITION | none | 0x0 |
_TRISD_RD0_SIZE | none | 0x1 |
_TRISD_RD0_LENGTH | none | 0x1 |
_TRISD_RD0_MASK | none | 0x1 |
_TRISD_RD1_POSN | none | 0x1 |
_TRISD_RD1_POSITION | none | 0x1 |
_TRISD_RD1_SIZE | none | 0x1 |
_TRISD_RD1_LENGTH | none | 0x1 |
_TRISD_RD1_MASK | none | 0x2 |
_TRISD_RD2_POSN | none | 0x2 |
_TRISD_RD2_POSITION | none | 0x2 |
_TRISD_RD2_SIZE | none | 0x1 |
_TRISD_RD2_LENGTH | none | 0x1 |
_TRISD_RD2_MASK | none | 0x4 |
_TRISD_RD3_POSN | none | 0x3 |
_TRISD_RD3_POSITION | none | 0x3 |
_TRISD_RD3_SIZE | none | 0x1 |
_TRISD_RD3_LENGTH | none | 0x1 |
_TRISD_RD3_MASK | none | 0x8 |
_TRISD_RD4_POSN | none | 0x4 |
_TRISD_RD4_POSITION | none | 0x4 |
_TRISD_RD4_SIZE | none | 0x1 |
_TRISD_RD4_LENGTH | none | 0x1 |
_TRISD_RD4_MASK | none | 0x10 |
_TRISD_RD5_POSN | none | 0x5 |
_TRISD_RD5_POSITION | none | 0x5 |
_TRISD_RD5_SIZE | none | 0x1 |
_TRISD_RD5_LENGTH | none | 0x1 |
_TRISD_RD5_MASK | none | 0x20 |
_TRISD_RD6_POSN | none | 0x6 |
_TRISD_RD6_POSITION | none | 0x6 |
_TRISD_RD6_SIZE | none | 0x1 |
_TRISD_RD6_LENGTH | none | 0x1 |
_TRISD_RD6_MASK | none | 0x40 |
_TRISD_RD7_POSN | none | 0x7 |
_TRISD_RD7_POSITION | none | 0x7 |
_TRISD_RD7_SIZE | none | 0x1 |
_TRISD_RD7_LENGTH | none | 0x1 |
_TRISD_RD7_MASK | none | 0x80 |
_DDRD_TRISD0_POSN | none | 0x0 |
_DDRD_TRISD0_POSITION | none | 0x0 |
_DDRD_TRISD0_SIZE | none | 0x1 |
_DDRD_TRISD0_LENGTH | none | 0x1 |
_DDRD_TRISD0_MASK | none | 0x1 |
_DDRD_TRISD1_POSN | none | 0x1 |
_DDRD_TRISD1_POSITION | none | 0x1 |
_DDRD_TRISD1_SIZE | none | 0x1 |
_DDRD_TRISD1_LENGTH | none | 0x1 |
_DDRD_TRISD1_MASK | none | 0x2 |
_DDRD_TRISD2_POSN | none | 0x2 |
_DDRD_TRISD2_POSITION | none | 0x2 |
_DDRD_TRISD2_SIZE | none | 0x1 |
_DDRD_TRISD2_LENGTH | none | 0x1 |
_DDRD_TRISD2_MASK | none | 0x4 |
_DDRD_TRISD3_POSN | none | 0x3 |
_DDRD_TRISD3_POSITION | none | 0x3 |
_DDRD_TRISD3_SIZE | none | 0x1 |
_DDRD_TRISD3_LENGTH | none | 0x1 |
_DDRD_TRISD3_MASK | none | 0x8 |
_DDRD_TRISD4_POSN | none | 0x4 |
_DDRD_TRISD4_POSITION | none | 0x4 |
_DDRD_TRISD4_SIZE | none | 0x1 |
_DDRD_TRISD4_LENGTH | none | 0x1 |
_DDRD_TRISD4_MASK | none | 0x10 |
_DDRD_TRISD5_POSN | none | 0x5 |
_DDRD_TRISD5_POSITION | none | 0x5 |
_DDRD_TRISD5_SIZE | none | 0x1 |
_DDRD_TRISD5_LENGTH | none | 0x1 |
_DDRD_TRISD5_MASK | none | 0x20 |
_DDRD_TRISD6_POSN | none | 0x6 |
_DDRD_TRISD6_POSITION | none | 0x6 |
_DDRD_TRISD6_SIZE | none | 0x1 |
_DDRD_TRISD6_LENGTH | none | 0x1 |
_DDRD_TRISD6_MASK | none | 0x40 |
_DDRD_TRISD7_POSN | none | 0x7 |
_DDRD_TRISD7_POSITION | none | 0x7 |
_DDRD_TRISD7_SIZE | none | 0x1 |
_DDRD_TRISD7_LENGTH | none | 0x1 |
_DDRD_TRISD7_MASK | none | 0x80 |
_DDRD_RD0_POSN | none | 0x0 |
_DDRD_RD0_POSITION | none | 0x0 |
_DDRD_RD0_SIZE | none | 0x1 |
_DDRD_RD0_LENGTH | none | 0x1 |
_DDRD_RD0_MASK | none | 0x1 |
_DDRD_RD1_POSN | none | 0x1 |
_DDRD_RD1_POSITION | none | 0x1 |
_DDRD_RD1_SIZE | none | 0x1 |
_DDRD_RD1_LENGTH | none | 0x1 |
_DDRD_RD1_MASK | none | 0x2 |
_DDRD_RD2_POSN | none | 0x2 |
_DDRD_RD2_POSITION | none | 0x2 |
_DDRD_RD2_SIZE | none | 0x1 |
_DDRD_RD2_LENGTH | none | 0x1 |
_DDRD_RD2_MASK | none | 0x4 |
_DDRD_RD3_POSN | none | 0x3 |
_DDRD_RD3_POSITION | none | 0x3 |
_DDRD_RD3_SIZE | none | 0x1 |
_DDRD_RD3_LENGTH | none | 0x1 |
_DDRD_RD3_MASK | none | 0x8 |
_DDRD_RD4_POSN | none | 0x4 |
_DDRD_RD4_POSITION | none | 0x4 |
_DDRD_RD4_SIZE | none | 0x1 |
_DDRD_RD4_LENGTH | none | 0x1 |
_DDRD_RD4_MASK | none | 0x10 |
_DDRD_RD5_POSN | none | 0x5 |
_DDRD_RD5_POSITION | none | 0x5 |
_DDRD_RD5_SIZE | none | 0x1 |
_DDRD_RD5_LENGTH | none | 0x1 |
_DDRD_RD5_MASK | none | 0x20 |
_DDRD_RD6_POSN | none | 0x6 |
_DDRD_RD6_POSITION | none | 0x6 |
_DDRD_RD6_SIZE | none | 0x1 |
_DDRD_RD6_LENGTH | none | 0x1 |
_DDRD_RD6_MASK | none | 0x40 |
_DDRD_RD7_POSN | none | 0x7 |
_DDRD_RD7_POSITION | none | 0x7 |
_DDRD_RD7_SIZE | none | 0x1 |
_DDRD_RD7_LENGTH | none | 0x1 |
_DDRD_RD7_MASK | none | 0x80 |
_TRISE_TRISE0_POSN | none | 0x0 |
_TRISE_TRISE0_POSITION | none | 0x0 |
_TRISE_TRISE0_SIZE | none | 0x1 |
_TRISE_TRISE0_LENGTH | none | 0x1 |
_TRISE_TRISE0_MASK | none | 0x1 |
_TRISE_TRISE1_POSN | none | 0x1 |
_TRISE_TRISE1_POSITION | none | 0x1 |
_TRISE_TRISE1_SIZE | none | 0x1 |
_TRISE_TRISE1_LENGTH | none | 0x1 |
_TRISE_TRISE1_MASK | none | 0x2 |
_TRISE_TRISE2_POSN | none | 0x2 |
_TRISE_TRISE2_POSITION | none | 0x2 |
_TRISE_TRISE2_SIZE | none | 0x1 |
_TRISE_TRISE2_LENGTH | none | 0x1 |
_TRISE_TRISE2_MASK | none | 0x4 |
_TRISE_RE0_POSN | none | 0x0 |
_TRISE_RE0_POSITION | none | 0x0 |
_TRISE_RE0_SIZE | none | 0x1 |
_TRISE_RE0_LENGTH | none | 0x1 |
_TRISE_RE0_MASK | none | 0x1 |
_TRISE_RE1_POSN | none | 0x1 |
_TRISE_RE1_POSITION | none | 0x1 |
_TRISE_RE1_SIZE | none | 0x1 |
_TRISE_RE1_LENGTH | none | 0x1 |
_TRISE_RE1_MASK | none | 0x2 |
_TRISE_RE2_POSN | none | 0x2 |
_TRISE_RE2_POSITION | none | 0x2 |
_TRISE_RE2_SIZE | none | 0x1 |
_TRISE_RE2_LENGTH | none | 0x1 |
_TRISE_RE2_MASK | none | 0x4 |
_DDRE_TRISE0_POSN | none | 0x0 |
_DDRE_TRISE0_POSITION | none | 0x0 |
_DDRE_TRISE0_SIZE | none | 0x1 |
_DDRE_TRISE0_LENGTH | none | 0x1 |
_DDRE_TRISE0_MASK | none | 0x1 |
_DDRE_TRISE1_POSN | none | 0x1 |
_DDRE_TRISE1_POSITION | none | 0x1 |
_DDRE_TRISE1_SIZE | none | 0x1 |
_DDRE_TRISE1_LENGTH | none | 0x1 |
_DDRE_TRISE1_MASK | none | 0x2 |
_DDRE_TRISE2_POSN | none | 0x2 |
_DDRE_TRISE2_POSITION | none | 0x2 |
_DDRE_TRISE2_SIZE | none | 0x1 |
_DDRE_TRISE2_LENGTH | none | 0x1 |
_DDRE_TRISE2_MASK | none | 0x4 |
_DDRE_RE0_POSN | none | 0x0 |
_DDRE_RE0_POSITION | none | 0x0 |
_DDRE_RE0_SIZE | none | 0x1 |
_DDRE_RE0_LENGTH | none | 0x1 |
_DDRE_RE0_MASK | none | 0x1 |
_DDRE_RE1_POSN | none | 0x1 |
_DDRE_RE1_POSITION | none | 0x1 |
_DDRE_RE1_SIZE | none | 0x1 |
_DDRE_RE1_LENGTH | none | 0x1 |
_DDRE_RE1_MASK | none | 0x2 |
_DDRE_RE2_POSN | none | 0x2 |
_DDRE_RE2_POSITION | none | 0x2 |
_DDRE_RE2_SIZE | none | 0x1 |
_DDRE_RE2_LENGTH | none | 0x1 |
_DDRE_RE2_MASK | none | 0x4 |
_OSCTUNE_TUN_POSN | none | 0x0 |
_OSCTUNE_TUN_POSITION | none | 0x0 |
_OSCTUNE_TUN_SIZE | none | 0x5 |
_OSCTUNE_TUN_LENGTH | none | 0x5 |
_OSCTUNE_TUN_MASK | none | 0x1F |
_OSCTUNE_INTSRC_POSN | none | 0x7 |
_OSCTUNE_INTSRC_POSITION | none | 0x7 |
_OSCTUNE_INTSRC_SIZE | none | 0x1 |
_OSCTUNE_INTSRC_LENGTH | none | 0x1 |
_OSCTUNE_INTSRC_MASK | none | 0x80 |
_OSCTUNE_TUN0_POSN | none | 0x0 |
_OSCTUNE_TUN0_POSITION | none | 0x0 |
_OSCTUNE_TUN0_SIZE | none | 0x1 |
_OSCTUNE_TUN0_LENGTH | none | 0x1 |
_OSCTUNE_TUN0_MASK | none | 0x1 |
_OSCTUNE_TUN1_POSN | none | 0x1 |
_OSCTUNE_TUN1_POSITION | none | 0x1 |
_OSCTUNE_TUN1_SIZE | none | 0x1 |
_OSCTUNE_TUN1_LENGTH | none | 0x1 |
_OSCTUNE_TUN1_MASK | none | 0x2 |
_OSCTUNE_TUN2_POSN | none | 0x2 |
_OSCTUNE_TUN2_POSITION | none | 0x2 |
_OSCTUNE_TUN2_SIZE | none | 0x1 |
_OSCTUNE_TUN2_LENGTH | none | 0x1 |
_OSCTUNE_TUN2_MASK | none | 0x4 |
_OSCTUNE_TUN3_POSN | none | 0x3 |
_OSCTUNE_TUN3_POSITION | none | 0x3 |
_OSCTUNE_TUN3_SIZE | none | 0x1 |
_OSCTUNE_TUN3_LENGTH | none | 0x1 |
_OSCTUNE_TUN3_MASK | none | 0x8 |
_OSCTUNE_TUN4_POSN | none | 0x4 |
_OSCTUNE_TUN4_POSITION | none | 0x4 |
_OSCTUNE_TUN4_SIZE | none | 0x1 |
_OSCTUNE_TUN4_LENGTH | none | 0x1 |
_OSCTUNE_TUN4_MASK | none | 0x10 |
_PIE1_TMR1IE_POSN | none | 0x0 |
_PIE1_TMR1IE_POSITION | none | 0x0 |
_PIE1_TMR1IE_SIZE | none | 0x1 |
_PIE1_TMR1IE_LENGTH | none | 0x1 |
_PIE1_TMR1IE_MASK | none | 0x1 |
_PIE1_TMR2IE_POSN | none | 0x1 |
_PIE1_TMR2IE_POSITION | none | 0x1 |
_PIE1_TMR2IE_SIZE | none | 0x1 |
_PIE1_TMR2IE_LENGTH | none | 0x1 |
_PIE1_TMR2IE_MASK | none | 0x2 |
_PIE1_CCP1IE_POSN | none | 0x2 |
_PIE1_CCP1IE_POSITION | none | 0x2 |
_PIE1_CCP1IE_SIZE | none | 0x1 |
_PIE1_CCP1IE_LENGTH | none | 0x1 |
_PIE1_CCP1IE_MASK | none | 0x4 |
_PIE1_SSPIE_POSN | none | 0x3 |
_PIE1_SSPIE_POSITION | none | 0x3 |
_PIE1_SSPIE_SIZE | none | 0x1 |
_PIE1_SSPIE_LENGTH | none | 0x1 |
_PIE1_SSPIE_MASK | none | 0x8 |
_PIE1_TXIE_POSN | none | 0x4 |
_PIE1_TXIE_POSITION | none | 0x4 |
_PIE1_TXIE_SIZE | none | 0x1 |
_PIE1_TXIE_LENGTH | none | 0x1 |
_PIE1_TXIE_MASK | none | 0x10 |
_PIE1_RCIE_POSN | none | 0x5 |
_PIE1_RCIE_POSITION | none | 0x5 |
_PIE1_RCIE_SIZE | none | 0x1 |
_PIE1_RCIE_LENGTH | none | 0x1 |
_PIE1_RCIE_MASK | none | 0x20 |
_PIE1_ADIE_POSN | none | 0x6 |
_PIE1_ADIE_POSITION | none | 0x6 |
_PIE1_ADIE_SIZE | none | 0x1 |
_PIE1_ADIE_LENGTH | none | 0x1 |
_PIE1_ADIE_MASK | none | 0x40 |
_PIE1_SPPIE_POSN | none | 0x7 |
_PIE1_SPPIE_POSITION | none | 0x7 |
_PIE1_SPPIE_SIZE | none | 0x1 |
_PIE1_SPPIE_LENGTH | none | 0x1 |
_PIE1_SPPIE_MASK | none | 0x80 |
_PIE1_PSPIE_POSN | none | 0x7 |
_PIE1_PSPIE_POSITION | none | 0x7 |
_PIE1_PSPIE_SIZE | none | 0x1 |
_PIE1_PSPIE_LENGTH | none | 0x1 |
_PIE1_PSPIE_MASK | none | 0x80 |
_PIE1_RC1IE_POSN | none | 0x5 |
_PIE1_RC1IE_POSITION | none | 0x5 |
_PIE1_RC1IE_SIZE | none | 0x1 |
_PIE1_RC1IE_LENGTH | none | 0x1 |
_PIE1_RC1IE_MASK | none | 0x20 |
_PIE1_TX1IE_POSN | none | 0x4 |
_PIE1_TX1IE_POSITION | none | 0x4 |
_PIE1_TX1IE_SIZE | none | 0x1 |
_PIE1_TX1IE_LENGTH | none | 0x1 |
_PIE1_TX1IE_MASK | none | 0x10 |
_PIR1_TMR1IF_POSN | none | 0x0 |
_PIR1_TMR1IF_POSITION | none | 0x0 |
_PIR1_TMR1IF_SIZE | none | 0x1 |
_PIR1_TMR1IF_LENGTH | none | 0x1 |
_PIR1_TMR1IF_MASK | none | 0x1 |
_PIR1_TMR2IF_POSN | none | 0x1 |
_PIR1_TMR2IF_POSITION | none | 0x1 |
_PIR1_TMR2IF_SIZE | none | 0x1 |
_PIR1_TMR2IF_LENGTH | none | 0x1 |
_PIR1_TMR2IF_MASK | none | 0x2 |
_PIR1_CCP1IF_POSN | none | 0x2 |
_PIR1_CCP1IF_POSITION | none | 0x2 |
_PIR1_CCP1IF_SIZE | none | 0x1 |
_PIR1_CCP1IF_LENGTH | none | 0x1 |
_PIR1_CCP1IF_MASK | none | 0x4 |
_PIR1_SSPIF_POSN | none | 0x3 |
_PIR1_SSPIF_POSITION | none | 0x3 |
_PIR1_SSPIF_SIZE | none | 0x1 |
_PIR1_SSPIF_LENGTH | none | 0x1 |
_PIR1_SSPIF_MASK | none | 0x8 |
_PIR1_TXIF_POSN | none | 0x4 |
_PIR1_TXIF_POSITION | none | 0x4 |
_PIR1_TXIF_SIZE | none | 0x1 |
_PIR1_TXIF_LENGTH | none | 0x1 |
_PIR1_TXIF_MASK | none | 0x10 |
_PIR1_RCIF_POSN | none | 0x5 |
_PIR1_RCIF_POSITION | none | 0x5 |
_PIR1_RCIF_SIZE | none | 0x1 |
_PIR1_RCIF_LENGTH | none | 0x1 |
_PIR1_RCIF_MASK | none | 0x20 |
_PIR1_ADIF_POSN | none | 0x6 |
_PIR1_ADIF_POSITION | none | 0x6 |
_PIR1_ADIF_SIZE | none | 0x1 |
_PIR1_ADIF_LENGTH | none | 0x1 |
_PIR1_ADIF_MASK | none | 0x40 |
_PIR1_SPPIF_POSN | none | 0x7 |
_PIR1_SPPIF_POSITION | none | 0x7 |
_PIR1_SPPIF_SIZE | none | 0x1 |
_PIR1_SPPIF_LENGTH | none | 0x1 |
_PIR1_SPPIF_MASK | none | 0x80 |
_PIR1_PSPIF_POSN | none | 0x7 |
_PIR1_PSPIF_POSITION | none | 0x7 |
_PIR1_PSPIF_SIZE | none | 0x1 |
_PIR1_PSPIF_LENGTH | none | 0x1 |
_PIR1_PSPIF_MASK | none | 0x80 |
_PIR1_RC1IF_POSN | none | 0x5 |
_PIR1_RC1IF_POSITION | none | 0x5 |
_PIR1_RC1IF_SIZE | none | 0x1 |
_PIR1_RC1IF_LENGTH | none | 0x1 |
_PIR1_RC1IF_MASK | none | 0x20 |
_PIR1_TX1IF_POSN | none | 0x4 |
_PIR1_TX1IF_POSITION | none | 0x4 |
_PIR1_TX1IF_SIZE | none | 0x1 |
_PIR1_TX1IF_LENGTH | none | 0x1 |
_PIR1_TX1IF_MASK | none | 0x10 |
_IPR1_TMR1IP_POSN | none | 0x0 |
_IPR1_TMR1IP_POSITION | none | 0x0 |
_IPR1_TMR1IP_SIZE | none | 0x1 |
_IPR1_TMR1IP_LENGTH | none | 0x1 |
_IPR1_TMR1IP_MASK | none | 0x1 |
_IPR1_TMR2IP_POSN | none | 0x1 |
_IPR1_TMR2IP_POSITION | none | 0x1 |
_IPR1_TMR2IP_SIZE | none | 0x1 |
_IPR1_TMR2IP_LENGTH | none | 0x1 |
_IPR1_TMR2IP_MASK | none | 0x2 |
_IPR1_CCP1IP_POSN | none | 0x2 |
_IPR1_CCP1IP_POSITION | none | 0x2 |
_IPR1_CCP1IP_SIZE | none | 0x1 |
_IPR1_CCP1IP_LENGTH | none | 0x1 |
_IPR1_CCP1IP_MASK | none | 0x4 |
_IPR1_SSPIP_POSN | none | 0x3 |
_IPR1_SSPIP_POSITION | none | 0x3 |
_IPR1_SSPIP_SIZE | none | 0x1 |
_IPR1_SSPIP_LENGTH | none | 0x1 |
_IPR1_SSPIP_MASK | none | 0x8 |
_IPR1_TXIP_POSN | none | 0x4 |
_IPR1_TXIP_POSITION | none | 0x4 |
_IPR1_TXIP_SIZE | none | 0x1 |
_IPR1_TXIP_LENGTH | none | 0x1 |
_IPR1_TXIP_MASK | none | 0x10 |
_IPR1_RCIP_POSN | none | 0x5 |
_IPR1_RCIP_POSITION | none | 0x5 |
_IPR1_RCIP_SIZE | none | 0x1 |
_IPR1_RCIP_LENGTH | none | 0x1 |
_IPR1_RCIP_MASK | none | 0x20 |
_IPR1_ADIP_POSN | none | 0x6 |
_IPR1_ADIP_POSITION | none | 0x6 |
_IPR1_ADIP_SIZE | none | 0x1 |
_IPR1_ADIP_LENGTH | none | 0x1 |
_IPR1_ADIP_MASK | none | 0x40 |
_IPR1_SPPIP_POSN | none | 0x7 |
_IPR1_SPPIP_POSITION | none | 0x7 |
_IPR1_SPPIP_SIZE | none | 0x1 |
_IPR1_SPPIP_LENGTH | none | 0x1 |
_IPR1_SPPIP_MASK | none | 0x80 |
_IPR1_PSPIP_POSN | none | 0x7 |
_IPR1_PSPIP_POSITION | none | 0x7 |
_IPR1_PSPIP_SIZE | none | 0x1 |
_IPR1_PSPIP_LENGTH | none | 0x1 |
_IPR1_PSPIP_MASK | none | 0x80 |
_IPR1_RC1IP_POSN | none | 0x5 |
_IPR1_RC1IP_POSITION | none | 0x5 |
_IPR1_RC1IP_SIZE | none | 0x1 |
_IPR1_RC1IP_LENGTH | none | 0x1 |
_IPR1_RC1IP_MASK | none | 0x20 |
_IPR1_TX1IP_POSN | none | 0x4 |
_IPR1_TX1IP_POSITION | none | 0x4 |
_IPR1_TX1IP_SIZE | none | 0x1 |
_IPR1_TX1IP_LENGTH | none | 0x1 |
_IPR1_TX1IP_MASK | none | 0x10 |
_PIE2_CCP2IE_POSN | none | 0x0 |
_PIE2_CCP2IE_POSITION | none | 0x0 |
_PIE2_CCP2IE_SIZE | none | 0x1 |
_PIE2_CCP2IE_LENGTH | none | 0x1 |
_PIE2_CCP2IE_MASK | none | 0x1 |
_PIE2_TMR3IE_POSN | none | 0x1 |
_PIE2_TMR3IE_POSITION | none | 0x1 |
_PIE2_TMR3IE_SIZE | none | 0x1 |
_PIE2_TMR3IE_LENGTH | none | 0x1 |
_PIE2_TMR3IE_MASK | none | 0x2 |
_PIE2_HLVDIE_POSN | none | 0x2 |
_PIE2_HLVDIE_POSITION | none | 0x2 |
_PIE2_HLVDIE_SIZE | none | 0x1 |
_PIE2_HLVDIE_LENGTH | none | 0x1 |
_PIE2_HLVDIE_MASK | none | 0x4 |
_PIE2_BCLIE_POSN | none | 0x3 |
_PIE2_BCLIE_POSITION | none | 0x3 |
_PIE2_BCLIE_SIZE | none | 0x1 |
_PIE2_BCLIE_LENGTH | none | 0x1 |
_PIE2_BCLIE_MASK | none | 0x8 |
_PIE2_EEIE_POSN | none | 0x4 |
_PIE2_EEIE_POSITION | none | 0x4 |
_PIE2_EEIE_SIZE | none | 0x1 |
_PIE2_EEIE_LENGTH | none | 0x1 |
_PIE2_EEIE_MASK | none | 0x10 |
_PIE2_USBIE_POSN | none | 0x5 |
_PIE2_USBIE_POSITION | none | 0x5 |
_PIE2_USBIE_SIZE | none | 0x1 |
_PIE2_USBIE_LENGTH | none | 0x1 |
_PIE2_USBIE_MASK | none | 0x20 |
_PIE2_CMIE_POSN | none | 0x6 |
_PIE2_CMIE_POSITION | none | 0x6 |
_PIE2_CMIE_SIZE | none | 0x1 |
_PIE2_CMIE_LENGTH | none | 0x1 |
_PIE2_CMIE_MASK | none | 0x40 |
_PIE2_OSCFIE_POSN | none | 0x7 |
_PIE2_OSCFIE_POSITION | none | 0x7 |
_PIE2_OSCFIE_SIZE | none | 0x1 |
_PIE2_OSCFIE_LENGTH | none | 0x1 |
_PIE2_OSCFIE_MASK | none | 0x80 |
_PIE2_LVDIE_POSN | none | 0x2 |
_PIE2_LVDIE_POSITION | none | 0x2 |
_PIE2_LVDIE_SIZE | none | 0x1 |
_PIE2_LVDIE_LENGTH | none | 0x1 |
_PIE2_LVDIE_MASK | none | 0x4 |
_PIR2_CCP2IF_POSN | none | 0x0 |
_PIR2_CCP2IF_POSITION | none | 0x0 |
_PIR2_CCP2IF_SIZE | none | 0x1 |
_PIR2_CCP2IF_LENGTH | none | 0x1 |
_PIR2_CCP2IF_MASK | none | 0x1 |
_PIR2_TMR3IF_POSN | none | 0x1 |
_PIR2_TMR3IF_POSITION | none | 0x1 |
_PIR2_TMR3IF_SIZE | none | 0x1 |
_PIR2_TMR3IF_LENGTH | none | 0x1 |
_PIR2_TMR3IF_MASK | none | 0x2 |
_PIR2_HLVDIF_POSN | none | 0x2 |
_PIR2_HLVDIF_POSITION | none | 0x2 |
_PIR2_HLVDIF_SIZE | none | 0x1 |
_PIR2_HLVDIF_LENGTH | none | 0x1 |
_PIR2_HLVDIF_MASK | none | 0x4 |
_PIR2_BCLIF_POSN | none | 0x3 |
_PIR2_BCLIF_POSITION | none | 0x3 |
_PIR2_BCLIF_SIZE | none | 0x1 |
_PIR2_BCLIF_LENGTH | none | 0x1 |
_PIR2_BCLIF_MASK | none | 0x8 |
_PIR2_EEIF_POSN | none | 0x4 |
_PIR2_EEIF_POSITION | none | 0x4 |
_PIR2_EEIF_SIZE | none | 0x1 |
_PIR2_EEIF_LENGTH | none | 0x1 |
_PIR2_EEIF_MASK | none | 0x10 |
_PIR2_USBIF_POSN | none | 0x5 |
_PIR2_USBIF_POSITION | none | 0x5 |
_PIR2_USBIF_SIZE | none | 0x1 |
_PIR2_USBIF_LENGTH | none | 0x1 |
_PIR2_USBIF_MASK | none | 0x20 |
_PIR2_CMIF_POSN | none | 0x6 |
_PIR2_CMIF_POSITION | none | 0x6 |
_PIR2_CMIF_SIZE | none | 0x1 |
_PIR2_CMIF_LENGTH | none | 0x1 |
_PIR2_CMIF_MASK | none | 0x40 |
_PIR2_OSCFIF_POSN | none | 0x7 |
_PIR2_OSCFIF_POSITION | none | 0x7 |
_PIR2_OSCFIF_SIZE | none | 0x1 |
_PIR2_OSCFIF_LENGTH | none | 0x1 |
_PIR2_OSCFIF_MASK | none | 0x80 |
_PIR2_LVDIF_POSN | none | 0x2 |
_PIR2_LVDIF_POSITION | none | 0x2 |
_PIR2_LVDIF_SIZE | none | 0x1 |
_PIR2_LVDIF_LENGTH | none | 0x1 |
_PIR2_LVDIF_MASK | none | 0x4 |
_IPR2_CCP2IP_POSN | none | 0x0 |
_IPR2_CCP2IP_POSITION | none | 0x0 |
_IPR2_CCP2IP_SIZE | none | 0x1 |
_IPR2_CCP2IP_LENGTH | none | 0x1 |
_IPR2_CCP2IP_MASK | none | 0x1 |
_IPR2_TMR3IP_POSN | none | 0x1 |
_IPR2_TMR3IP_POSITION | none | 0x1 |
_IPR2_TMR3IP_SIZE | none | 0x1 |
_IPR2_TMR3IP_LENGTH | none | 0x1 |
_IPR2_TMR3IP_MASK | none | 0x2 |
_IPR2_HLVDIP_POSN | none | 0x2 |
_IPR2_HLVDIP_POSITION | none | 0x2 |
_IPR2_HLVDIP_SIZE | none | 0x1 |
_IPR2_HLVDIP_LENGTH | none | 0x1 |
_IPR2_HLVDIP_MASK | none | 0x4 |
_IPR2_BCLIP_POSN | none | 0x3 |
_IPR2_BCLIP_POSITION | none | 0x3 |
_IPR2_BCLIP_SIZE | none | 0x1 |
_IPR2_BCLIP_LENGTH | none | 0x1 |
_IPR2_BCLIP_MASK | none | 0x8 |
_IPR2_EEIP_POSN | none | 0x4 |
_IPR2_EEIP_POSITION | none | 0x4 |
_IPR2_EEIP_SIZE | none | 0x1 |
_IPR2_EEIP_LENGTH | none | 0x1 |
_IPR2_EEIP_MASK | none | 0x10 |
_IPR2_USBIP_POSN | none | 0x5 |
_IPR2_USBIP_POSITION | none | 0x5 |
_IPR2_USBIP_SIZE | none | 0x1 |
_IPR2_USBIP_LENGTH | none | 0x1 |
_IPR2_USBIP_MASK | none | 0x20 |
_IPR2_CMIP_POSN | none | 0x6 |
_IPR2_CMIP_POSITION | none | 0x6 |
_IPR2_CMIP_SIZE | none | 0x1 |
_IPR2_CMIP_LENGTH | none | 0x1 |
_IPR2_CMIP_MASK | none | 0x40 |
_IPR2_OSCFIP_POSN | none | 0x7 |
_IPR2_OSCFIP_POSITION | none | 0x7 |
_IPR2_OSCFIP_SIZE | none | 0x1 |
_IPR2_OSCFIP_LENGTH | none | 0x1 |
_IPR2_OSCFIP_MASK | none | 0x80 |
_IPR2_LVDIP_POSN | none | 0x2 |
_IPR2_LVDIP_POSITION | none | 0x2 |
_IPR2_LVDIP_SIZE | none | 0x1 |
_IPR2_LVDIP_LENGTH | none | 0x1 |
_IPR2_LVDIP_MASK | none | 0x4 |
_EECON1_RD_POSN | none | 0x0 |
_EECON1_RD_POSITION | none | 0x0 |
_EECON1_RD_SIZE | none | 0x1 |
_EECON1_RD_LENGTH | none | 0x1 |
_EECON1_RD_MASK | none | 0x1 |
_EECON1_WR_POSN | none | 0x1 |
_EECON1_WR_POSITION | none | 0x1 |
_EECON1_WR_SIZE | none | 0x1 |
_EECON1_WR_LENGTH | none | 0x1 |
_EECON1_WR_MASK | none | 0x2 |
_EECON1_WREN_POSN | none | 0x2 |
_EECON1_WREN_POSITION | none | 0x2 |
_EECON1_WREN_SIZE | none | 0x1 |
_EECON1_WREN_LENGTH | none | 0x1 |
_EECON1_WREN_MASK | none | 0x4 |
_EECON1_WRERR_POSN | none | 0x3 |
_EECON1_WRERR_POSITION | none | 0x3 |
_EECON1_WRERR_SIZE | none | 0x1 |
_EECON1_WRERR_LENGTH | none | 0x1 |
_EECON1_WRERR_MASK | none | 0x8 |
_EECON1_FREE_POSN | none | 0x4 |
_EECON1_FREE_POSITION | none | 0x4 |
_EECON1_FREE_SIZE | none | 0x1 |
_EECON1_FREE_LENGTH | none | 0x1 |
_EECON1_FREE_MASK | none | 0x10 |
_EECON1_CFGS_POSN | none | 0x6 |
_EECON1_CFGS_POSITION | none | 0x6 |
_EECON1_CFGS_SIZE | none | 0x1 |
_EECON1_CFGS_LENGTH | none | 0x1 |
_EECON1_CFGS_MASK | none | 0x40 |
_EECON1_EEPGD_POSN | none | 0x7 |
_EECON1_EEPGD_POSITION | none | 0x7 |
_EECON1_EEPGD_SIZE | none | 0x1 |
_EECON1_EEPGD_LENGTH | none | 0x1 |
_EECON1_EEPGD_MASK | none | 0x80 |
_EECON1_EEFS_POSN | none | 0x6 |
_EECON1_EEFS_POSITION | none | 0x6 |
_EECON1_EEFS_SIZE | none | 0x1 |
_EECON1_EEFS_LENGTH | none | 0x1 |
_EECON1_EEFS_MASK | none | 0x40 |
_RCSTA_RX9D_POSN | none | 0x0 |
_RCSTA_RX9D_POSITION | none | 0x0 |
_RCSTA_RX9D_SIZE | none | 0x1 |
_RCSTA_RX9D_LENGTH | none | 0x1 |
_RCSTA_RX9D_MASK | none | 0x1 |
_RCSTA_OERR_POSN | none | 0x1 |
_RCSTA_OERR_POSITION | none | 0x1 |
_RCSTA_OERR_SIZE | none | 0x1 |
_RCSTA_OERR_LENGTH | none | 0x1 |
_RCSTA_OERR_MASK | none | 0x2 |
_RCSTA_FERR_POSN | none | 0x2 |
_RCSTA_FERR_POSITION | none | 0x2 |
_RCSTA_FERR_SIZE | none | 0x1 |
_RCSTA_FERR_LENGTH | none | 0x1 |
_RCSTA_FERR_MASK | none | 0x4 |
_RCSTA_ADDEN_POSN | none | 0x3 |
_RCSTA_ADDEN_POSITION | none | 0x3 |
_RCSTA_ADDEN_SIZE | none | 0x1 |
_RCSTA_ADDEN_LENGTH | none | 0x1 |
_RCSTA_ADDEN_MASK | none | 0x8 |
_RCSTA_CREN_POSN | none | 0x4 |
_RCSTA_CREN_POSITION | none | 0x4 |
_RCSTA_CREN_SIZE | none | 0x1 |
_RCSTA_CREN_LENGTH | none | 0x1 |
_RCSTA_CREN_MASK | none | 0x10 |
_RCSTA_SREN_POSN | none | 0x5 |
_RCSTA_SREN_POSITION | none | 0x5 |
_RCSTA_SREN_SIZE | none | 0x1 |
_RCSTA_SREN_LENGTH | none | 0x1 |
_RCSTA_SREN_MASK | none | 0x20 |
_RCSTA_RX9_POSN | none | 0x6 |
_RCSTA_RX9_POSITION | none | 0x6 |
_RCSTA_RX9_SIZE | none | 0x1 |
_RCSTA_RX9_LENGTH | none | 0x1 |
_RCSTA_RX9_MASK | none | 0x40 |
_RCSTA_SPEN_POSN | none | 0x7 |
_RCSTA_SPEN_POSITION | none | 0x7 |
_RCSTA_SPEN_SIZE | none | 0x1 |
_RCSTA_SPEN_LENGTH | none | 0x1 |
_RCSTA_SPEN_MASK | none | 0x80 |
_RCSTA_ADEN_POSN | none | 0x3 |
_RCSTA_ADEN_POSITION | none | 0x3 |
_RCSTA_ADEN_SIZE | none | 0x1 |
_RCSTA_ADEN_LENGTH | none | 0x1 |
_RCSTA_ADEN_MASK | none | 0x8 |
_RCSTA_SRENA_POSN | none | 0x5 |
_RCSTA_SRENA_POSITION | none | 0x5 |
_RCSTA_SRENA_SIZE | none | 0x1 |
_RCSTA_SRENA_LENGTH | none | 0x1 |
_RCSTA_SRENA_MASK | none | 0x20 |
_RCSTA_RC8_9_POSN | none | 0x6 |
_RCSTA_RC8_9_POSITION | none | 0x6 |
_RCSTA_RC8_9_SIZE | none | 0x1 |
_RCSTA_RC8_9_LENGTH | none | 0x1 |
_RCSTA_RC8_9_MASK | none | 0x40 |
_RCSTA_RC9_POSN | none | 0x6 |
_RCSTA_RC9_POSITION | none | 0x6 |
_RCSTA_RC9_SIZE | none | 0x1 |
_RCSTA_RC9_LENGTH | none | 0x1 |
_RCSTA_RC9_MASK | none | 0x40 |
_RCSTA_RCD8_POSN | none | 0x0 |
_RCSTA_RCD8_POSITION | none | 0x0 |
_RCSTA_RCD8_SIZE | none | 0x1 |
_RCSTA_RCD8_LENGTH | none | 0x1 |
_RCSTA_RCD8_MASK | none | 0x1 |
_RCSTA1_RX9D_POSN | none | 0x0 |
_RCSTA1_RX9D_POSITION | none | 0x0 |
_RCSTA1_RX9D_SIZE | none | 0x1 |
_RCSTA1_RX9D_LENGTH | none | 0x1 |
_RCSTA1_RX9D_MASK | none | 0x1 |
_RCSTA1_OERR_POSN | none | 0x1 |
_RCSTA1_OERR_POSITION | none | 0x1 |
_RCSTA1_OERR_SIZE | none | 0x1 |
_RCSTA1_OERR_LENGTH | none | 0x1 |
_RCSTA1_OERR_MASK | none | 0x2 |
_RCSTA1_FERR_POSN | none | 0x2 |
_RCSTA1_FERR_POSITION | none | 0x2 |
_RCSTA1_FERR_SIZE | none | 0x1 |
_RCSTA1_FERR_LENGTH | none | 0x1 |
_RCSTA1_FERR_MASK | none | 0x4 |
_RCSTA1_ADDEN_POSN | none | 0x3 |
_RCSTA1_ADDEN_POSITION | none | 0x3 |
_RCSTA1_ADDEN_SIZE | none | 0x1 |
_RCSTA1_ADDEN_LENGTH | none | 0x1 |
_RCSTA1_ADDEN_MASK | none | 0x8 |
_RCSTA1_CREN_POSN | none | 0x4 |
_RCSTA1_CREN_POSITION | none | 0x4 |
_RCSTA1_CREN_SIZE | none | 0x1 |
_RCSTA1_CREN_LENGTH | none | 0x1 |
_RCSTA1_CREN_MASK | none | 0x10 |
_RCSTA1_SREN_POSN | none | 0x5 |
_RCSTA1_SREN_POSITION | none | 0x5 |
_RCSTA1_SREN_SIZE | none | 0x1 |
_RCSTA1_SREN_LENGTH | none | 0x1 |
_RCSTA1_SREN_MASK | none | 0x20 |
_RCSTA1_RX9_POSN | none | 0x6 |
_RCSTA1_RX9_POSITION | none | 0x6 |
_RCSTA1_RX9_SIZE | none | 0x1 |
_RCSTA1_RX9_LENGTH | none | 0x1 |
_RCSTA1_RX9_MASK | none | 0x40 |
_RCSTA1_SPEN_POSN | none | 0x7 |
_RCSTA1_SPEN_POSITION | none | 0x7 |
_RCSTA1_SPEN_SIZE | none | 0x1 |
_RCSTA1_SPEN_LENGTH | none | 0x1 |
_RCSTA1_SPEN_MASK | none | 0x80 |
_RCSTA1_ADEN_POSN | none | 0x3 |
_RCSTA1_ADEN_POSITION | none | 0x3 |
_RCSTA1_ADEN_SIZE | none | 0x1 |
_RCSTA1_ADEN_LENGTH | none | 0x1 |
_RCSTA1_ADEN_MASK | none | 0x8 |
_RCSTA1_SRENA_POSN | none | 0x5 |
_RCSTA1_SRENA_POSITION | none | 0x5 |
_RCSTA1_SRENA_SIZE | none | 0x1 |
_RCSTA1_SRENA_LENGTH | none | 0x1 |
_RCSTA1_SRENA_MASK | none | 0x20 |
_RCSTA1_RC8_9_POSN | none | 0x6 |
_RCSTA1_RC8_9_POSITION | none | 0x6 |
_RCSTA1_RC8_9_SIZE | none | 0x1 |
_RCSTA1_RC8_9_LENGTH | none | 0x1 |
_RCSTA1_RC8_9_MASK | none | 0x40 |
_RCSTA1_RC9_POSN | none | 0x6 |
_RCSTA1_RC9_POSITION | none | 0x6 |
_RCSTA1_RC9_SIZE | none | 0x1 |
_RCSTA1_RC9_LENGTH | none | 0x1 |
_RCSTA1_RC9_MASK | none | 0x40 |
_RCSTA1_RCD8_POSN | none | 0x0 |
_RCSTA1_RCD8_POSITION | none | 0x0 |
_RCSTA1_RCD8_SIZE | none | 0x1 |
_RCSTA1_RCD8_LENGTH | none | 0x1 |
_RCSTA1_RCD8_MASK | none | 0x1 |
_TXSTA_TX9D_POSN | none | 0x0 |
_TXSTA_TX9D_POSITION | none | 0x0 |
_TXSTA_TX9D_SIZE | none | 0x1 |
_TXSTA_TX9D_LENGTH | none | 0x1 |
_TXSTA_TX9D_MASK | none | 0x1 |
_TXSTA_TRMT_POSN | none | 0x1 |
_TXSTA_TRMT_POSITION | none | 0x1 |
_TXSTA_TRMT_SIZE | none | 0x1 |
_TXSTA_TRMT_LENGTH | none | 0x1 |
_TXSTA_TRMT_MASK | none | 0x2 |
_TXSTA_BRGH_POSN | none | 0x2 |
_TXSTA_BRGH_POSITION | none | 0x2 |
_TXSTA_BRGH_SIZE | none | 0x1 |
_TXSTA_BRGH_LENGTH | none | 0x1 |
_TXSTA_BRGH_MASK | none | 0x4 |
_TXSTA_SENDB_POSN | none | 0x3 |
_TXSTA_SENDB_POSITION | none | 0x3 |
_TXSTA_SENDB_SIZE | none | 0x1 |
_TXSTA_SENDB_LENGTH | none | 0x1 |
_TXSTA_SENDB_MASK | none | 0x8 |
_TXSTA_SYNC_POSN | none | 0x4 |
_TXSTA_SYNC_POSITION | none | 0x4 |
_TXSTA_SYNC_SIZE | none | 0x1 |
_TXSTA_SYNC_LENGTH | none | 0x1 |
_TXSTA_SYNC_MASK | none | 0x10 |
_TXSTA_TXEN_POSN | none | 0x5 |
_TXSTA_TXEN_POSITION | none | 0x5 |
_TXSTA_TXEN_SIZE | none | 0x1 |
_TXSTA_TXEN_LENGTH | none | 0x1 |
_TXSTA_TXEN_MASK | none | 0x20 |
_TXSTA_TX9_POSN | none | 0x6 |
_TXSTA_TX9_POSITION | none | 0x6 |
_TXSTA_TX9_SIZE | none | 0x1 |
_TXSTA_TX9_LENGTH | none | 0x1 |
_TXSTA_TX9_MASK | none | 0x40 |
_TXSTA_CSRC_POSN | none | 0x7 |
_TXSTA_CSRC_POSITION | none | 0x7 |
_TXSTA_CSRC_SIZE | none | 0x1 |
_TXSTA_CSRC_LENGTH | none | 0x1 |
_TXSTA_CSRC_MASK | none | 0x80 |
_TXSTA_BRGH1_POSN | none | 0x2 |
_TXSTA_BRGH1_POSITION | none | 0x2 |
_TXSTA_BRGH1_SIZE | none | 0x1 |
_TXSTA_BRGH1_LENGTH | none | 0x1 |
_TXSTA_BRGH1_MASK | none | 0x4 |
_TXSTA_CSRC1_POSN | none | 0x7 |
_TXSTA_CSRC1_POSITION | none | 0x7 |
_TXSTA_CSRC1_SIZE | none | 0x1 |
_TXSTA_CSRC1_LENGTH | none | 0x1 |
_TXSTA_CSRC1_MASK | none | 0x80 |
_TXSTA_SENDB1_POSN | none | 0x3 |
_TXSTA_SENDB1_POSITION | none | 0x3 |
_TXSTA_SENDB1_SIZE | none | 0x1 |
_TXSTA_SENDB1_LENGTH | none | 0x1 |
_TXSTA_SENDB1_MASK | none | 0x8 |
_TXSTA_SYNC1_POSN | none | 0x4 |
_TXSTA_SYNC1_POSITION | none | 0x4 |
_TXSTA_SYNC1_SIZE | none | 0x1 |
_TXSTA_SYNC1_LENGTH | none | 0x1 |
_TXSTA_SYNC1_MASK | none | 0x10 |
_TXSTA_TRMT1_POSN | none | 0x1 |
_TXSTA_TRMT1_POSITION | none | 0x1 |
_TXSTA_TRMT1_SIZE | none | 0x1 |
_TXSTA_TRMT1_LENGTH | none | 0x1 |
_TXSTA_TRMT1_MASK | none | 0x2 |
_TXSTA_TX91_POSN | none | 0x6 |
_TXSTA_TX91_POSITION | none | 0x6 |
_TXSTA_TX91_SIZE | none | 0x1 |
_TXSTA_TX91_LENGTH | none | 0x1 |
_TXSTA_TX91_MASK | none | 0x40 |
_TXSTA_TX9D1_POSN | none | 0x0 |
_TXSTA_TX9D1_POSITION | none | 0x0 |
_TXSTA_TX9D1_SIZE | none | 0x1 |
_TXSTA_TX9D1_LENGTH | none | 0x1 |
_TXSTA_TX9D1_MASK | none | 0x1 |
_TXSTA_TXEN1_POSN | none | 0x5 |
_TXSTA_TXEN1_POSITION | none | 0x5 |
_TXSTA_TXEN1_SIZE | none | 0x1 |
_TXSTA_TXEN1_LENGTH | none | 0x1 |
_TXSTA_TXEN1_MASK | none | 0x20 |
_TXSTA_TX8_9_POSN | none | 0x6 |
_TXSTA_TX8_9_POSITION | none | 0x6 |
_TXSTA_TX8_9_SIZE | none | 0x1 |
_TXSTA_TX8_9_LENGTH | none | 0x1 |
_TXSTA_TX8_9_MASK | none | 0x40 |
_TXSTA_TXD8_POSN | none | 0x0 |
_TXSTA_TXD8_POSITION | none | 0x0 |
_TXSTA_TXD8_SIZE | none | 0x1 |
_TXSTA_TXD8_LENGTH | none | 0x1 |
_TXSTA_TXD8_MASK | none | 0x1 |
_TXSTA1_TX9D_POSN | none | 0x0 |
_TXSTA1_TX9D_POSITION | none | 0x0 |
_TXSTA1_TX9D_SIZE | none | 0x1 |
_TXSTA1_TX9D_LENGTH | none | 0x1 |
_TXSTA1_TX9D_MASK | none | 0x1 |
_TXSTA1_TRMT_POSN | none | 0x1 |
_TXSTA1_TRMT_POSITION | none | 0x1 |
_TXSTA1_TRMT_SIZE | none | 0x1 |
_TXSTA1_TRMT_LENGTH | none | 0x1 |
_TXSTA1_TRMT_MASK | none | 0x2 |
_TXSTA1_BRGH_POSN | none | 0x2 |
_TXSTA1_BRGH_POSITION | none | 0x2 |
_TXSTA1_BRGH_SIZE | none | 0x1 |
_TXSTA1_BRGH_LENGTH | none | 0x1 |
_TXSTA1_BRGH_MASK | none | 0x4 |
_TXSTA1_SENDB_POSN | none | 0x3 |
_TXSTA1_SENDB_POSITION | none | 0x3 |
_TXSTA1_SENDB_SIZE | none | 0x1 |
_TXSTA1_SENDB_LENGTH | none | 0x1 |
_TXSTA1_SENDB_MASK | none | 0x8 |
_TXSTA1_SYNC_POSN | none | 0x4 |
_TXSTA1_SYNC_POSITION | none | 0x4 |
_TXSTA1_SYNC_SIZE | none | 0x1 |
_TXSTA1_SYNC_LENGTH | none | 0x1 |
_TXSTA1_SYNC_MASK | none | 0x10 |
_TXSTA1_TXEN_POSN | none | 0x5 |
_TXSTA1_TXEN_POSITION | none | 0x5 |
_TXSTA1_TXEN_SIZE | none | 0x1 |
_TXSTA1_TXEN_LENGTH | none | 0x1 |
_TXSTA1_TXEN_MASK | none | 0x20 |
_TXSTA1_TX9_POSN | none | 0x6 |
_TXSTA1_TX9_POSITION | none | 0x6 |
_TXSTA1_TX9_SIZE | none | 0x1 |
_TXSTA1_TX9_LENGTH | none | 0x1 |
_TXSTA1_TX9_MASK | none | 0x40 |
_TXSTA1_CSRC_POSN | none | 0x7 |
_TXSTA1_CSRC_POSITION | none | 0x7 |
_TXSTA1_CSRC_SIZE | none | 0x1 |
_TXSTA1_CSRC_LENGTH | none | 0x1 |
_TXSTA1_CSRC_MASK | none | 0x80 |
_TXSTA1_BRGH1_POSN | none | 0x2 |
_TXSTA1_BRGH1_POSITION | none | 0x2 |
_TXSTA1_BRGH1_SIZE | none | 0x1 |
_TXSTA1_BRGH1_LENGTH | none | 0x1 |
_TXSTA1_BRGH1_MASK | none | 0x4 |
_TXSTA1_CSRC1_POSN | none | 0x7 |
_TXSTA1_CSRC1_POSITION | none | 0x7 |
_TXSTA1_CSRC1_SIZE | none | 0x1 |
_TXSTA1_CSRC1_LENGTH | none | 0x1 |
_TXSTA1_CSRC1_MASK | none | 0x80 |
_TXSTA1_SENDB1_POSN | none | 0x3 |
_TXSTA1_SENDB1_POSITION | none | 0x3 |
_TXSTA1_SENDB1_SIZE | none | 0x1 |
_TXSTA1_SENDB1_LENGTH | none | 0x1 |
_TXSTA1_SENDB1_MASK | none | 0x8 |
_TXSTA1_SYNC1_POSN | none | 0x4 |
_TXSTA1_SYNC1_POSITION | none | 0x4 |
_TXSTA1_SYNC1_SIZE | none | 0x1 |
_TXSTA1_SYNC1_LENGTH | none | 0x1 |
_TXSTA1_SYNC1_MASK | none | 0x10 |
_TXSTA1_TRMT1_POSN | none | 0x1 |
_TXSTA1_TRMT1_POSITION | none | 0x1 |
_TXSTA1_TRMT1_SIZE | none | 0x1 |
_TXSTA1_TRMT1_LENGTH | none | 0x1 |
_TXSTA1_TRMT1_MASK | none | 0x2 |
_TXSTA1_TX91_POSN | none | 0x6 |
_TXSTA1_TX91_POSITION | none | 0x6 |
_TXSTA1_TX91_SIZE | none | 0x1 |
_TXSTA1_TX91_LENGTH | none | 0x1 |
_TXSTA1_TX91_MASK | none | 0x40 |
_TXSTA1_TX9D1_POSN | none | 0x0 |
_TXSTA1_TX9D1_POSITION | none | 0x0 |
_TXSTA1_TX9D1_SIZE | none | 0x1 |
_TXSTA1_TX9D1_LENGTH | none | 0x1 |
_TXSTA1_TX9D1_MASK | none | 0x1 |
_TXSTA1_TXEN1_POSN | none | 0x5 |
_TXSTA1_TXEN1_POSITION | none | 0x5 |
_TXSTA1_TXEN1_SIZE | none | 0x1 |
_TXSTA1_TXEN1_LENGTH | none | 0x1 |
_TXSTA1_TXEN1_MASK | none | 0x20 |
_TXSTA1_TX8_9_POSN | none | 0x6 |
_TXSTA1_TX8_9_POSITION | none | 0x6 |
_TXSTA1_TX8_9_SIZE | none | 0x1 |
_TXSTA1_TX8_9_LENGTH | none | 0x1 |
_TXSTA1_TX8_9_MASK | none | 0x40 |
_TXSTA1_TXD8_POSN | none | 0x0 |
_TXSTA1_TXD8_POSITION | none | 0x0 |
_TXSTA1_TXD8_SIZE | none | 0x1 |
_TXSTA1_TXD8_LENGTH | none | 0x1 |
_TXSTA1_TXD8_MASK | none | 0x1 |
_T3CON_NOT_T3SYNC_POSN | none | 0x2 |
_T3CON_NOT_T3SYNC_POSITION | none | 0x2 |
_T3CON_NOT_T3SYNC_SIZE | none | 0x1 |
_T3CON_NOT_T3SYNC_LENGTH | none | 0x1 |
_T3CON_NOT_T3SYNC_MASK | none | 0x4 |
_T3CON_TMR3ON_POSN | none | 0x0 |
_T3CON_TMR3ON_POSITION | none | 0x0 |
_T3CON_TMR3ON_SIZE | none | 0x1 |
_T3CON_TMR3ON_LENGTH | none | 0x1 |
_T3CON_TMR3ON_MASK | none | 0x1 |
_T3CON_TMR3CS_POSN | none | 0x1 |
_T3CON_TMR3CS_POSITION | none | 0x1 |
_T3CON_TMR3CS_SIZE | none | 0x1 |
_T3CON_TMR3CS_LENGTH | none | 0x1 |
_T3CON_TMR3CS_MASK | none | 0x2 |
_T3CON_nT3SYNC_POSN | none | 0x2 |
_T3CON_nT3SYNC_POSITION | none | 0x2 |
_T3CON_nT3SYNC_SIZE | none | 0x1 |
_T3CON_nT3SYNC_LENGTH | none | 0x1 |
_T3CON_nT3SYNC_MASK | none | 0x4 |
_T3CON_T3CCP1_POSN | none | 0x3 |
_T3CON_T3CCP1_POSITION | none | 0x3 |
_T3CON_T3CCP1_SIZE | none | 0x1 |
_T3CON_T3CCP1_LENGTH | none | 0x1 |
_T3CON_T3CCP1_MASK | none | 0x8 |
_T3CON_T3CKPS_POSN | none | 0x4 |
_T3CON_T3CKPS_POSITION | none | 0x4 |
_T3CON_T3CKPS_SIZE | none | 0x2 |
_T3CON_T3CKPS_LENGTH | none | 0x2 |
_T3CON_T3CKPS_MASK | none | 0x30 |
_T3CON_T3CCP2_POSN | none | 0x6 |
_T3CON_T3CCP2_POSITION | none | 0x6 |
_T3CON_T3CCP2_SIZE | none | 0x1 |
_T3CON_T3CCP2_LENGTH | none | 0x1 |
_T3CON_T3CCP2_MASK | none | 0x40 |
_T3CON_RD16_POSN | none | 0x7 |
_T3CON_RD16_POSITION | none | 0x7 |
_T3CON_RD16_SIZE | none | 0x1 |
_T3CON_RD16_LENGTH | none | 0x1 |
_T3CON_RD16_MASK | none | 0x80 |
_T3CON_T3SYNC_POSN | none | 0x2 |
_T3CON_T3SYNC_POSITION | none | 0x2 |
_T3CON_T3SYNC_SIZE | none | 0x1 |
_T3CON_T3SYNC_LENGTH | none | 0x1 |
_T3CON_T3SYNC_MASK | none | 0x4 |
_T3CON_T3CKPS0_POSN | none | 0x4 |
_T3CON_T3CKPS0_POSITION | none | 0x4 |
_T3CON_T3CKPS0_SIZE | none | 0x1 |
_T3CON_T3CKPS0_LENGTH | none | 0x1 |
_T3CON_T3CKPS0_MASK | none | 0x10 |
_T3CON_T3CKPS1_POSN | none | 0x5 |
_T3CON_T3CKPS1_POSITION | none | 0x5 |
_T3CON_T3CKPS1_SIZE | none | 0x1 |
_T3CON_T3CKPS1_LENGTH | none | 0x1 |
_T3CON_T3CKPS1_MASK | none | 0x20 |
_T3CON_T3NSYNC_POSN | none | 0x2 |
_T3CON_T3NSYNC_POSITION | none | 0x2 |
_T3CON_T3NSYNC_SIZE | none | 0x1 |
_T3CON_T3NSYNC_LENGTH | none | 0x1 |
_T3CON_T3NSYNC_MASK | none | 0x4 |
_T3CON_RD163_POSN | none | 0x7 |
_T3CON_RD163_POSITION | none | 0x7 |
_T3CON_RD163_SIZE | none | 0x1 |
_T3CON_RD163_LENGTH | none | 0x1 |
_T3CON_RD163_MASK | none | 0x80 |
_T3CON_SOSCEN3_POSN | none | 0x3 |
_T3CON_SOSCEN3_POSITION | none | 0x3 |
_T3CON_SOSCEN3_SIZE | none | 0x1 |
_T3CON_SOSCEN3_LENGTH | none | 0x1 |
_T3CON_SOSCEN3_MASK | none | 0x8 |
_T3CON_T3RD16_POSN | none | 0x7 |
_T3CON_T3RD16_POSITION | none | 0x7 |
_T3CON_T3RD16_SIZE | none | 0x1 |
_T3CON_T3RD16_LENGTH | none | 0x1 |
_T3CON_T3RD16_MASK | none | 0x80 |
_CMCON_CM_POSN | none | 0x0 |
_CMCON_CM_POSITION | none | 0x0 |
_CMCON_CM_SIZE | none | 0x3 |
_CMCON_CM_LENGTH | none | 0x3 |
_CMCON_CM_MASK | none | 0x7 |
_CMCON_CIS_POSN | none | 0x3 |
_CMCON_CIS_POSITION | none | 0x3 |
_CMCON_CIS_SIZE | none | 0x1 |
_CMCON_CIS_LENGTH | none | 0x1 |
_CMCON_CIS_MASK | none | 0x8 |
_CMCON_C1INV_POSN | none | 0x4 |
_CMCON_C1INV_POSITION | none | 0x4 |
_CMCON_C1INV_SIZE | none | 0x1 |
_CMCON_C1INV_LENGTH | none | 0x1 |
_CMCON_C1INV_MASK | none | 0x10 |
_CMCON_C2INV_POSN | none | 0x5 |
_CMCON_C2INV_POSITION | none | 0x5 |
_CMCON_C2INV_SIZE | none | 0x1 |
_CMCON_C2INV_LENGTH | none | 0x1 |
_CMCON_C2INV_MASK | none | 0x20 |
_CMCON_C1OUT_POSN | none | 0x6 |
_CMCON_C1OUT_POSITION | none | 0x6 |
_CMCON_C1OUT_SIZE | none | 0x1 |
_CMCON_C1OUT_LENGTH | none | 0x1 |
_CMCON_C1OUT_MASK | none | 0x40 |
_CMCON_C2OUT_POSN | none | 0x7 |
_CMCON_C2OUT_POSITION | none | 0x7 |
_CMCON_C2OUT_SIZE | none | 0x1 |
_CMCON_C2OUT_LENGTH | none | 0x1 |
_CMCON_C2OUT_MASK | none | 0x80 |
_CMCON_CM0_POSN | none | 0x0 |
_CMCON_CM0_POSITION | none | 0x0 |
_CMCON_CM0_SIZE | none | 0x1 |
_CMCON_CM0_LENGTH | none | 0x1 |
_CMCON_CM0_MASK | none | 0x1 |
_CMCON_CM1_POSN | none | 0x1 |
_CMCON_CM1_POSITION | none | 0x1 |
_CMCON_CM1_SIZE | none | 0x1 |
_CMCON_CM1_LENGTH | none | 0x1 |
_CMCON_CM1_MASK | none | 0x2 |
_CMCON_CM2_POSN | none | 0x2 |
_CMCON_CM2_POSITION | none | 0x2 |
_CMCON_CM2_SIZE | none | 0x1 |
_CMCON_CM2_LENGTH | none | 0x1 |
_CMCON_CM2_MASK | none | 0x4 |
_CMCON_CMEN0_POSN | none | 0x0 |
_CMCON_CMEN0_POSITION | none | 0x0 |
_CMCON_CMEN0_SIZE | none | 0x1 |
_CMCON_CMEN0_LENGTH | none | 0x1 |
_CMCON_CMEN0_MASK | none | 0x1 |
_CMCON_CMEN1_POSN | none | 0x1 |
_CMCON_CMEN1_POSITION | none | 0x1 |
_CMCON_CMEN1_SIZE | none | 0x1 |
_CMCON_CMEN1_LENGTH | none | 0x1 |
_CMCON_CMEN1_MASK | none | 0x2 |
_CMCON_CMEN2_POSN | none | 0x2 |
_CMCON_CMEN2_POSITION | none | 0x2 |
_CMCON_CMEN2_SIZE | none | 0x1 |
_CMCON_CMEN2_LENGTH | none | 0x1 |
_CMCON_CMEN2_MASK | none | 0x4 |
_CVRCON_CVR_POSN | none | 0x0 |
_CVRCON_CVR_POSITION | none | 0x0 |
_CVRCON_CVR_SIZE | none | 0x4 |
_CVRCON_CVR_LENGTH | none | 0x4 |
_CVRCON_CVR_MASK | none | 0xF |
_CVRCON_CVRSS_POSN | none | 0x4 |
_CVRCON_CVRSS_POSITION | none | 0x4 |
_CVRCON_CVRSS_SIZE | none | 0x1 |
_CVRCON_CVRSS_LENGTH | none | 0x1 |
_CVRCON_CVRSS_MASK | none | 0x10 |
_CVRCON_CVRR_POSN | none | 0x5 |
_CVRCON_CVRR_POSITION | none | 0x5 |
_CVRCON_CVRR_SIZE | none | 0x1 |
_CVRCON_CVRR_LENGTH | none | 0x1 |
_CVRCON_CVRR_MASK | none | 0x20 |
_CVRCON_CVROE_POSN | none | 0x6 |
_CVRCON_CVROE_POSITION | none | 0x6 |
_CVRCON_CVROE_SIZE | none | 0x1 |
_CVRCON_CVROE_LENGTH | none | 0x1 |
_CVRCON_CVROE_MASK | none | 0x40 |
_CVRCON_CVREN_POSN | none | 0x7 |
_CVRCON_CVREN_POSITION | none | 0x7 |
_CVRCON_CVREN_SIZE | none | 0x1 |
_CVRCON_CVREN_LENGTH | none | 0x1 |
_CVRCON_CVREN_MASK | none | 0x80 |
_CVRCON_CVR0_POSN | none | 0x0 |
_CVRCON_CVR0_POSITION | none | 0x0 |
_CVRCON_CVR0_SIZE | none | 0x1 |
_CVRCON_CVR0_LENGTH | none | 0x1 |
_CVRCON_CVR0_MASK | none | 0x1 |
_CVRCON_CVR1_POSN | none | 0x1 |
_CVRCON_CVR1_POSITION | none | 0x1 |
_CVRCON_CVR1_SIZE | none | 0x1 |
_CVRCON_CVR1_LENGTH | none | 0x1 |
_CVRCON_CVR1_MASK | none | 0x2 |
_CVRCON_CVR2_POSN | none | 0x2 |
_CVRCON_CVR2_POSITION | none | 0x2 |
_CVRCON_CVR2_SIZE | none | 0x1 |
_CVRCON_CVR2_LENGTH | none | 0x1 |
_CVRCON_CVR2_MASK | none | 0x4 |
_CVRCON_CVR3_POSN | none | 0x3 |
_CVRCON_CVR3_POSITION | none | 0x3 |
_CVRCON_CVR3_SIZE | none | 0x1 |
_CVRCON_CVR3_LENGTH | none | 0x1 |
_CVRCON_CVR3_MASK | none | 0x8 |
_CVRCON_CVREF_POSN | none | 0x4 |
_CVRCON_CVREF_POSITION | none | 0x4 |
_CVRCON_CVREF_SIZE | none | 0x1 |
_CVRCON_CVREF_LENGTH | none | 0x1 |
_CVRCON_CVREF_MASK | none | 0x10 |
_CVRCON_CVROEN_POSN | none | 0x6 |
_CVRCON_CVROEN_POSITION | none | 0x6 |
_CVRCON_CVROEN_SIZE | none | 0x1 |
_CVRCON_CVROEN_LENGTH | none | 0x1 |
_CVRCON_CVROEN_MASK | none | 0x40 |
_ECCP1AS_PSSBD_POSN | none | 0x0 |
_ECCP1AS_PSSBD_POSITION | none | 0x0 |
_ECCP1AS_PSSBD_SIZE | none | 0x2 |
_ECCP1AS_PSSBD_LENGTH | none | 0x2 |
_ECCP1AS_PSSBD_MASK | none | 0x3 |
_ECCP1AS_PSSAC_POSN | none | 0x2 |
_ECCP1AS_PSSAC_POSITION | none | 0x2 |
_ECCP1AS_PSSAC_SIZE | none | 0x2 |
_ECCP1AS_PSSAC_LENGTH | none | 0x2 |
_ECCP1AS_PSSAC_MASK | none | 0xC |
_ECCP1AS_ECCPAS_POSN | none | 0x4 |
_ECCP1AS_ECCPAS_POSITION | none | 0x4 |
_ECCP1AS_ECCPAS_SIZE | none | 0x3 |
_ECCP1AS_ECCPAS_LENGTH | none | 0x3 |
_ECCP1AS_ECCPAS_MASK | none | 0x70 |
_ECCP1AS_ECCPASE_POSN | none | 0x7 |
_ECCP1AS_ECCPASE_POSITION | none | 0x7 |
_ECCP1AS_ECCPASE_SIZE | none | 0x1 |
_ECCP1AS_ECCPASE_LENGTH | none | 0x1 |
_ECCP1AS_ECCPASE_MASK | none | 0x80 |
_ECCP1AS_PSSBD0_POSN | none | 0x0 |
_ECCP1AS_PSSBD0_POSITION | none | 0x0 |
_ECCP1AS_PSSBD0_SIZE | none | 0x1 |
_ECCP1AS_PSSBD0_LENGTH | none | 0x1 |
_ECCP1AS_PSSBD0_MASK | none | 0x1 |
_ECCP1AS_PSSBD1_POSN | none | 0x1 |
_ECCP1AS_PSSBD1_POSITION | none | 0x1 |
_ECCP1AS_PSSBD1_SIZE | none | 0x1 |
_ECCP1AS_PSSBD1_LENGTH | none | 0x1 |
_ECCP1AS_PSSBD1_MASK | none | 0x2 |
_ECCP1AS_PSSAC0_POSN | none | 0x2 |
_ECCP1AS_PSSAC0_POSITION | none | 0x2 |
_ECCP1AS_PSSAC0_SIZE | none | 0x1 |
_ECCP1AS_PSSAC0_LENGTH | none | 0x1 |
_ECCP1AS_PSSAC0_MASK | none | 0x4 |
_ECCP1AS_PSSAC1_POSN | none | 0x3 |
_ECCP1AS_PSSAC1_POSITION | none | 0x3 |
_ECCP1AS_PSSAC1_SIZE | none | 0x1 |
_ECCP1AS_PSSAC1_LENGTH | none | 0x1 |
_ECCP1AS_PSSAC1_MASK | none | 0x8 |
_ECCP1AS_ECCPAS0_POSN | none | 0x4 |
_ECCP1AS_ECCPAS0_POSITION | none | 0x4 |
_ECCP1AS_ECCPAS0_SIZE | none | 0x1 |
_ECCP1AS_ECCPAS0_LENGTH | none | 0x1 |
_ECCP1AS_ECCPAS0_MASK | none | 0x10 |
_ECCP1AS_ECCPAS1_POSN | none | 0x5 |
_ECCP1AS_ECCPAS1_POSITION | none | 0x5 |
_ECCP1AS_ECCPAS1_SIZE | none | 0x1 |
_ECCP1AS_ECCPAS1_LENGTH | none | 0x1 |
_ECCP1AS_ECCPAS1_MASK | none | 0x20 |
_ECCP1AS_ECCPAS2_POSN | none | 0x6 |
_ECCP1AS_ECCPAS2_POSITION | none | 0x6 |
_ECCP1AS_ECCPAS2_SIZE | none | 0x1 |
_ECCP1AS_ECCPAS2_LENGTH | none | 0x1 |
_ECCP1AS_ECCPAS2_MASK | none | 0x40 |
_CCP1AS_PSSBD_POSN | none | 0x0 |
_CCP1AS_PSSBD_POSITION | none | 0x0 |
_CCP1AS_PSSBD_SIZE | none | 0x2 |
_CCP1AS_PSSBD_LENGTH | none | 0x2 |
_CCP1AS_PSSBD_MASK | none | 0x3 |
_CCP1AS_PSSAC_POSN | none | 0x2 |
_CCP1AS_PSSAC_POSITION | none | 0x2 |
_CCP1AS_PSSAC_SIZE | none | 0x2 |
_CCP1AS_PSSAC_LENGTH | none | 0x2 |
_CCP1AS_PSSAC_MASK | none | 0xC |
_CCP1AS_ECCPAS_POSN | none | 0x4 |
_CCP1AS_ECCPAS_POSITION | none | 0x4 |
_CCP1AS_ECCPAS_SIZE | none | 0x3 |
_CCP1AS_ECCPAS_LENGTH | none | 0x3 |
_CCP1AS_ECCPAS_MASK | none | 0x70 |
_CCP1AS_ECCPASE_POSN | none | 0x7 |
_CCP1AS_ECCPASE_POSITION | none | 0x7 |
_CCP1AS_ECCPASE_SIZE | none | 0x1 |
_CCP1AS_ECCPASE_LENGTH | none | 0x1 |
_CCP1AS_ECCPASE_MASK | none | 0x80 |
_CCP1AS_PSSBD0_POSN | none | 0x0 |
_CCP1AS_PSSBD0_POSITION | none | 0x0 |
_CCP1AS_PSSBD0_SIZE | none | 0x1 |
_CCP1AS_PSSBD0_LENGTH | none | 0x1 |
_CCP1AS_PSSBD0_MASK | none | 0x1 |
_CCP1AS_PSSBD1_POSN | none | 0x1 |
_CCP1AS_PSSBD1_POSITION | none | 0x1 |
_CCP1AS_PSSBD1_SIZE | none | 0x1 |
_CCP1AS_PSSBD1_LENGTH | none | 0x1 |
_CCP1AS_PSSBD1_MASK | none | 0x2 |
_CCP1AS_PSSAC0_POSN | none | 0x2 |
_CCP1AS_PSSAC0_POSITION | none | 0x2 |
_CCP1AS_PSSAC0_SIZE | none | 0x1 |
_CCP1AS_PSSAC0_LENGTH | none | 0x1 |
_CCP1AS_PSSAC0_MASK | none | 0x4 |
_CCP1AS_PSSAC1_POSN | none | 0x3 |
_CCP1AS_PSSAC1_POSITION | none | 0x3 |
_CCP1AS_PSSAC1_SIZE | none | 0x1 |
_CCP1AS_PSSAC1_LENGTH | none | 0x1 |
_CCP1AS_PSSAC1_MASK | none | 0x8 |
_CCP1AS_ECCPAS0_POSN | none | 0x4 |
_CCP1AS_ECCPAS0_POSITION | none | 0x4 |
_CCP1AS_ECCPAS0_SIZE | none | 0x1 |
_CCP1AS_ECCPAS0_LENGTH | none | 0x1 |
_CCP1AS_ECCPAS0_MASK | none | 0x10 |
_CCP1AS_ECCPAS1_POSN | none | 0x5 |
_CCP1AS_ECCPAS1_POSITION | none | 0x5 |
_CCP1AS_ECCPAS1_SIZE | none | 0x1 |
_CCP1AS_ECCPAS1_LENGTH | none | 0x1 |
_CCP1AS_ECCPAS1_MASK | none | 0x20 |
_CCP1AS_ECCPAS2_POSN | none | 0x6 |
_CCP1AS_ECCPAS2_POSITION | none | 0x6 |
_CCP1AS_ECCPAS2_SIZE | none | 0x1 |
_CCP1AS_ECCPAS2_LENGTH | none | 0x1 |
_CCP1AS_ECCPAS2_MASK | none | 0x40 |
_ECCP1DEL_PDC_POSN | none | 0x0 |
_ECCP1DEL_PDC_POSITION | none | 0x0 |
_ECCP1DEL_PDC_SIZE | none | 0x7 |
_ECCP1DEL_PDC_LENGTH | none | 0x7 |
_ECCP1DEL_PDC_MASK | none | 0x7F |
_ECCP1DEL_PRSEN_POSN | none | 0x7 |
_ECCP1DEL_PRSEN_POSITION | none | 0x7 |
_ECCP1DEL_PRSEN_SIZE | none | 0x1 |
_ECCP1DEL_PRSEN_LENGTH | none | 0x1 |
_ECCP1DEL_PRSEN_MASK | none | 0x80 |
_ECCP1DEL_PDC0_POSN | none | 0x0 |
_ECCP1DEL_PDC0_POSITION | none | 0x0 |
_ECCP1DEL_PDC0_SIZE | none | 0x1 |
_ECCP1DEL_PDC0_LENGTH | none | 0x1 |
_ECCP1DEL_PDC0_MASK | none | 0x1 |
_ECCP1DEL_PDC1_POSN | none | 0x1 |
_ECCP1DEL_PDC1_POSITION | none | 0x1 |
_ECCP1DEL_PDC1_SIZE | none | 0x1 |
_ECCP1DEL_PDC1_LENGTH | none | 0x1 |
_ECCP1DEL_PDC1_MASK | none | 0x2 |
_ECCP1DEL_PDC2_POSN | none | 0x2 |
_ECCP1DEL_PDC2_POSITION | none | 0x2 |
_ECCP1DEL_PDC2_SIZE | none | 0x1 |
_ECCP1DEL_PDC2_LENGTH | none | 0x1 |
_ECCP1DEL_PDC2_MASK | none | 0x4 |
_ECCP1DEL_PDC3_POSN | none | 0x3 |
_ECCP1DEL_PDC3_POSITION | none | 0x3 |
_ECCP1DEL_PDC3_SIZE | none | 0x1 |
_ECCP1DEL_PDC3_LENGTH | none | 0x1 |
_ECCP1DEL_PDC3_MASK | none | 0x8 |
_ECCP1DEL_PDC4_POSN | none | 0x4 |
_ECCP1DEL_PDC4_POSITION | none | 0x4 |
_ECCP1DEL_PDC4_SIZE | none | 0x1 |
_ECCP1DEL_PDC4_LENGTH | none | 0x1 |
_ECCP1DEL_PDC4_MASK | none | 0x10 |
_ECCP1DEL_PDC5_POSN | none | 0x5 |
_ECCP1DEL_PDC5_POSITION | none | 0x5 |
_ECCP1DEL_PDC5_SIZE | none | 0x1 |
_ECCP1DEL_PDC5_LENGTH | none | 0x1 |
_ECCP1DEL_PDC5_MASK | none | 0x20 |
_ECCP1DEL_PDC6_POSN | none | 0x6 |
_ECCP1DEL_PDC6_POSITION | none | 0x6 |
_ECCP1DEL_PDC6_SIZE | none | 0x1 |
_ECCP1DEL_PDC6_LENGTH | none | 0x1 |
_ECCP1DEL_PDC6_MASK | none | 0x40 |
_CCP1DEL_PDC_POSN | none | 0x0 |
_CCP1DEL_PDC_POSITION | none | 0x0 |
_CCP1DEL_PDC_SIZE | none | 0x7 |
_CCP1DEL_PDC_LENGTH | none | 0x7 |
_CCP1DEL_PDC_MASK | none | 0x7F |
_CCP1DEL_PRSEN_POSN | none | 0x7 |
_CCP1DEL_PRSEN_POSITION | none | 0x7 |
_CCP1DEL_PRSEN_SIZE | none | 0x1 |
_CCP1DEL_PRSEN_LENGTH | none | 0x1 |
_CCP1DEL_PRSEN_MASK | none | 0x80 |
_CCP1DEL_PDC0_POSN | none | 0x0 |
_CCP1DEL_PDC0_POSITION | none | 0x0 |
_CCP1DEL_PDC0_SIZE | none | 0x1 |
_CCP1DEL_PDC0_LENGTH | none | 0x1 |
_CCP1DEL_PDC0_MASK | none | 0x1 |
_CCP1DEL_PDC1_POSN | none | 0x1 |
_CCP1DEL_PDC1_POSITION | none | 0x1 |
_CCP1DEL_PDC1_SIZE | none | 0x1 |
_CCP1DEL_PDC1_LENGTH | none | 0x1 |
_CCP1DEL_PDC1_MASK | none | 0x2 |
_CCP1DEL_PDC2_POSN | none | 0x2 |
_CCP1DEL_PDC2_POSITION | none | 0x2 |
_CCP1DEL_PDC2_SIZE | none | 0x1 |
_CCP1DEL_PDC2_LENGTH | none | 0x1 |
_CCP1DEL_PDC2_MASK | none | 0x4 |
_CCP1DEL_PDC3_POSN | none | 0x3 |
_CCP1DEL_PDC3_POSITION | none | 0x3 |
_CCP1DEL_PDC3_SIZE | none | 0x1 |
_CCP1DEL_PDC3_LENGTH | none | 0x1 |
_CCP1DEL_PDC3_MASK | none | 0x8 |
_CCP1DEL_PDC4_POSN | none | 0x4 |
_CCP1DEL_PDC4_POSITION | none | 0x4 |
_CCP1DEL_PDC4_SIZE | none | 0x1 |
_CCP1DEL_PDC4_LENGTH | none | 0x1 |
_CCP1DEL_PDC4_MASK | none | 0x10 |
_CCP1DEL_PDC5_POSN | none | 0x5 |
_CCP1DEL_PDC5_POSITION | none | 0x5 |
_CCP1DEL_PDC5_SIZE | none | 0x1 |
_CCP1DEL_PDC5_LENGTH | none | 0x1 |
_CCP1DEL_PDC5_MASK | none | 0x20 |
_CCP1DEL_PDC6_POSN | none | 0x6 |
_CCP1DEL_PDC6_POSITION | none | 0x6 |
_CCP1DEL_PDC6_SIZE | none | 0x1 |
_CCP1DEL_PDC6_LENGTH | none | 0x1 |
_CCP1DEL_PDC6_MASK | none | 0x40 |
_BAUDCON_ABDEN_POSN | none | 0x0 |
_BAUDCON_ABDEN_POSITION | none | 0x0 |
_BAUDCON_ABDEN_SIZE | none | 0x1 |
_BAUDCON_ABDEN_LENGTH | none | 0x1 |
_BAUDCON_ABDEN_MASK | none | 0x1 |
_BAUDCON_WUE_POSN | none | 0x1 |
_BAUDCON_WUE_POSITION | none | 0x1 |
_BAUDCON_WUE_SIZE | none | 0x1 |
_BAUDCON_WUE_LENGTH | none | 0x1 |
_BAUDCON_WUE_MASK | none | 0x2 |
_BAUDCON_BRG16_POSN | none | 0x3 |
_BAUDCON_BRG16_POSITION | none | 0x3 |
_BAUDCON_BRG16_SIZE | none | 0x1 |
_BAUDCON_BRG16_LENGTH | none | 0x1 |
_BAUDCON_BRG16_MASK | none | 0x8 |
_BAUDCON_TXCKP_POSN | none | 0x4 |
_BAUDCON_TXCKP_POSITION | none | 0x4 |
_BAUDCON_TXCKP_SIZE | none | 0x1 |
_BAUDCON_TXCKP_LENGTH | none | 0x1 |
_BAUDCON_TXCKP_MASK | none | 0x10 |
_BAUDCON_RXDTP_POSN | none | 0x5 |
_BAUDCON_RXDTP_POSITION | none | 0x5 |
_BAUDCON_RXDTP_SIZE | none | 0x1 |
_BAUDCON_RXDTP_LENGTH | none | 0x1 |
_BAUDCON_RXDTP_MASK | none | 0x20 |
_BAUDCON_RCIDL_POSN | none | 0x6 |
_BAUDCON_RCIDL_POSITION | none | 0x6 |
_BAUDCON_RCIDL_SIZE | none | 0x1 |
_BAUDCON_RCIDL_LENGTH | none | 0x1 |
_BAUDCON_RCIDL_MASK | none | 0x40 |
_BAUDCON_ABDOVF_POSN | none | 0x7 |
_BAUDCON_ABDOVF_POSITION | none | 0x7 |
_BAUDCON_ABDOVF_SIZE | none | 0x1 |
_BAUDCON_ABDOVF_LENGTH | none | 0x1 |
_BAUDCON_ABDOVF_MASK | none | 0x80 |
_BAUDCON_SCKP_POSN | none | 0x4 |
_BAUDCON_SCKP_POSITION | none | 0x4 |
_BAUDCON_SCKP_SIZE | none | 0x1 |
_BAUDCON_SCKP_LENGTH | none | 0x1 |
_BAUDCON_SCKP_MASK | none | 0x10 |
_BAUDCON_RCMT_POSN | none | 0x6 |
_BAUDCON_RCMT_POSITION | none | 0x6 |
_BAUDCON_RCMT_SIZE | none | 0x1 |
_BAUDCON_RCMT_LENGTH | none | 0x1 |
_BAUDCON_RCMT_MASK | none | 0x40 |
_BAUDCON_RXCKP_POSN | none | 0x5 |
_BAUDCON_RXCKP_POSITION | none | 0x5 |
_BAUDCON_RXCKP_SIZE | none | 0x1 |
_BAUDCON_RXCKP_LENGTH | none | 0x1 |
_BAUDCON_RXCKP_MASK | none | 0x20 |
_BAUDCON_W4E_POSN | none | 0x1 |
_BAUDCON_W4E_POSITION | none | 0x1 |
_BAUDCON_W4E_SIZE | none | 0x1 |
_BAUDCON_W4E_LENGTH | none | 0x1 |
_BAUDCON_W4E_MASK | none | 0x2 |
_BAUDCTL_ABDEN_POSN | none | 0x0 |
_BAUDCTL_ABDEN_POSITION | none | 0x0 |
_BAUDCTL_ABDEN_SIZE | none | 0x1 |
_BAUDCTL_ABDEN_LENGTH | none | 0x1 |
_BAUDCTL_ABDEN_MASK | none | 0x1 |
_BAUDCTL_WUE_POSN | none | 0x1 |
_BAUDCTL_WUE_POSITION | none | 0x1 |
_BAUDCTL_WUE_SIZE | none | 0x1 |
_BAUDCTL_WUE_LENGTH | none | 0x1 |
_BAUDCTL_WUE_MASK | none | 0x2 |
_BAUDCTL_BRG16_POSN | none | 0x3 |
_BAUDCTL_BRG16_POSITION | none | 0x3 |
_BAUDCTL_BRG16_SIZE | none | 0x1 |
_BAUDCTL_BRG16_LENGTH | none | 0x1 |
_BAUDCTL_BRG16_MASK | none | 0x8 |
_BAUDCTL_TXCKP_POSN | none | 0x4 |
_BAUDCTL_TXCKP_POSITION | none | 0x4 |
_BAUDCTL_TXCKP_SIZE | none | 0x1 |
_BAUDCTL_TXCKP_LENGTH | none | 0x1 |
_BAUDCTL_TXCKP_MASK | none | 0x10 |
_BAUDCTL_RXDTP_POSN | none | 0x5 |
_BAUDCTL_RXDTP_POSITION | none | 0x5 |
_BAUDCTL_RXDTP_SIZE | none | 0x1 |
_BAUDCTL_RXDTP_LENGTH | none | 0x1 |
_BAUDCTL_RXDTP_MASK | none | 0x20 |
_BAUDCTL_RCIDL_POSN | none | 0x6 |
_BAUDCTL_RCIDL_POSITION | none | 0x6 |
_BAUDCTL_RCIDL_SIZE | none | 0x1 |
_BAUDCTL_RCIDL_LENGTH | none | 0x1 |
_BAUDCTL_RCIDL_MASK | none | 0x40 |
_BAUDCTL_ABDOVF_POSN | none | 0x7 |
_BAUDCTL_ABDOVF_POSITION | none | 0x7 |
_BAUDCTL_ABDOVF_SIZE | none | 0x1 |
_BAUDCTL_ABDOVF_LENGTH | none | 0x1 |
_BAUDCTL_ABDOVF_MASK | none | 0x80 |
_BAUDCTL_SCKP_POSN | none | 0x4 |
_BAUDCTL_SCKP_POSITION | none | 0x4 |
_BAUDCTL_SCKP_SIZE | none | 0x1 |
_BAUDCTL_SCKP_LENGTH | none | 0x1 |
_BAUDCTL_SCKP_MASK | none | 0x10 |
_BAUDCTL_RCMT_POSN | none | 0x6 |
_BAUDCTL_RCMT_POSITION | none | 0x6 |
_BAUDCTL_RCMT_SIZE | none | 0x1 |
_BAUDCTL_RCMT_LENGTH | none | 0x1 |
_BAUDCTL_RCMT_MASK | none | 0x40 |
_BAUDCTL_RXCKP_POSN | none | 0x5 |
_BAUDCTL_RXCKP_POSITION | none | 0x5 |
_BAUDCTL_RXCKP_SIZE | none | 0x1 |
_BAUDCTL_RXCKP_LENGTH | none | 0x1 |
_BAUDCTL_RXCKP_MASK | none | 0x20 |
_BAUDCTL_W4E_POSN | none | 0x1 |
_BAUDCTL_W4E_POSITION | none | 0x1 |
_BAUDCTL_W4E_SIZE | none | 0x1 |
_BAUDCTL_W4E_LENGTH | none | 0x1 |
_BAUDCTL_W4E_MASK | none | 0x2 |
_CCP2CON_CCP2M_POSN | none | 0x0 |
_CCP2CON_CCP2M_POSITION | none | 0x0 |
_CCP2CON_CCP2M_SIZE | none | 0x4 |
_CCP2CON_CCP2M_LENGTH | none | 0x4 |
_CCP2CON_CCP2M_MASK | none | 0xF |
_CCP2CON_DC2B_POSN | none | 0x4 |
_CCP2CON_DC2B_POSITION | none | 0x4 |
_CCP2CON_DC2B_SIZE | none | 0x2 |
_CCP2CON_DC2B_LENGTH | none | 0x2 |
_CCP2CON_DC2B_MASK | none | 0x30 |
_CCP2CON_CCP2M0_POSN | none | 0x0 |
_CCP2CON_CCP2M0_POSITION | none | 0x0 |
_CCP2CON_CCP2M0_SIZE | none | 0x1 |
_CCP2CON_CCP2M0_LENGTH | none | 0x1 |
_CCP2CON_CCP2M0_MASK | none | 0x1 |
_CCP2CON_CCP2M1_POSN | none | 0x1 |
_CCP2CON_CCP2M1_POSITION | none | 0x1 |
_CCP2CON_CCP2M1_SIZE | none | 0x1 |
_CCP2CON_CCP2M1_LENGTH | none | 0x1 |
_CCP2CON_CCP2M1_MASK | none | 0x2 |
_CCP2CON_CCP2M2_POSN | none | 0x2 |
_CCP2CON_CCP2M2_POSITION | none | 0x2 |
_CCP2CON_CCP2M2_SIZE | none | 0x1 |
_CCP2CON_CCP2M2_LENGTH | none | 0x1 |
_CCP2CON_CCP2M2_MASK | none | 0x4 |
_CCP2CON_CCP2M3_POSN | none | 0x3 |
_CCP2CON_CCP2M3_POSITION | none | 0x3 |
_CCP2CON_CCP2M3_SIZE | none | 0x1 |
_CCP2CON_CCP2M3_LENGTH | none | 0x1 |
_CCP2CON_CCP2M3_MASK | none | 0x8 |
_CCP2CON_DC2B0_POSN | none | 0x4 |
_CCP2CON_DC2B0_POSITION | none | 0x4 |
_CCP2CON_DC2B0_SIZE | none | 0x1 |
_CCP2CON_DC2B0_LENGTH | none | 0x1 |
_CCP2CON_DC2B0_MASK | none | 0x10 |
_CCP2CON_DC2B1_POSN | none | 0x5 |
_CCP2CON_DC2B1_POSITION | none | 0x5 |
_CCP2CON_DC2B1_SIZE | none | 0x1 |
_CCP2CON_DC2B1_LENGTH | none | 0x1 |
_CCP2CON_DC2B1_MASK | none | 0x20 |
_CCP1CON_CCP1M_POSN | none | 0x0 |
_CCP1CON_CCP1M_POSITION | none | 0x0 |
_CCP1CON_CCP1M_SIZE | none | 0x4 |
_CCP1CON_CCP1M_LENGTH | none | 0x4 |
_CCP1CON_CCP1M_MASK | none | 0xF |
_CCP1CON_DC1B_POSN | none | 0x4 |
_CCP1CON_DC1B_POSITION | none | 0x4 |
_CCP1CON_DC1B_SIZE | none | 0x2 |
_CCP1CON_DC1B_LENGTH | none | 0x2 |
_CCP1CON_DC1B_MASK | none | 0x30 |
_CCP1CON_P1M_POSN | none | 0x6 |
_CCP1CON_P1M_POSITION | none | 0x6 |
_CCP1CON_P1M_SIZE | none | 0x2 |
_CCP1CON_P1M_LENGTH | none | 0x2 |
_CCP1CON_P1M_MASK | none | 0xC0 |
_CCP1CON_CCP1M0_POSN | none | 0x0 |
_CCP1CON_CCP1M0_POSITION | none | 0x0 |
_CCP1CON_CCP1M0_SIZE | none | 0x1 |
_CCP1CON_CCP1M0_LENGTH | none | 0x1 |
_CCP1CON_CCP1M0_MASK | none | 0x1 |
_CCP1CON_CCP1M1_POSN | none | 0x1 |
_CCP1CON_CCP1M1_POSITION | none | 0x1 |
_CCP1CON_CCP1M1_SIZE | none | 0x1 |
_CCP1CON_CCP1M1_LENGTH | none | 0x1 |
_CCP1CON_CCP1M1_MASK | none | 0x2 |
_CCP1CON_CCP1M2_POSN | none | 0x2 |
_CCP1CON_CCP1M2_POSITION | none | 0x2 |
_CCP1CON_CCP1M2_SIZE | none | 0x1 |
_CCP1CON_CCP1M2_LENGTH | none | 0x1 |
_CCP1CON_CCP1M2_MASK | none | 0x4 |
_CCP1CON_CCP1M3_POSN | none | 0x3 |
_CCP1CON_CCP1M3_POSITION | none | 0x3 |
_CCP1CON_CCP1M3_SIZE | none | 0x1 |
_CCP1CON_CCP1M3_LENGTH | none | 0x1 |
_CCP1CON_CCP1M3_MASK | none | 0x8 |
_CCP1CON_DC1B0_POSN | none | 0x4 |
_CCP1CON_DC1B0_POSITION | none | 0x4 |
_CCP1CON_DC1B0_SIZE | none | 0x1 |
_CCP1CON_DC1B0_LENGTH | none | 0x1 |
_CCP1CON_DC1B0_MASK | none | 0x10 |
_CCP1CON_DC1B1_POSN | none | 0x5 |
_CCP1CON_DC1B1_POSITION | none | 0x5 |
_CCP1CON_DC1B1_SIZE | none | 0x1 |
_CCP1CON_DC1B1_LENGTH | none | 0x1 |
_CCP1CON_DC1B1_MASK | none | 0x20 |
_CCP1CON_P1M0_POSN | none | 0x6 |
_CCP1CON_P1M0_POSITION | none | 0x6 |
_CCP1CON_P1M0_SIZE | none | 0x1 |
_CCP1CON_P1M0_LENGTH | none | 0x1 |
_CCP1CON_P1M0_MASK | none | 0x40 |
_CCP1CON_P1M1_POSN | none | 0x7 |
_CCP1CON_P1M1_POSITION | none | 0x7 |
_CCP1CON_P1M1_SIZE | none | 0x1 |
_CCP1CON_P1M1_LENGTH | none | 0x1 |
_CCP1CON_P1M1_MASK | none | 0x80 |
_ECCP1CON_CCP1M_POSN | none | 0x0 |
_ECCP1CON_CCP1M_POSITION | none | 0x0 |
_ECCP1CON_CCP1M_SIZE | none | 0x4 |
_ECCP1CON_CCP1M_LENGTH | none | 0x4 |
_ECCP1CON_CCP1M_MASK | none | 0xF |
_ECCP1CON_DC1B_POSN | none | 0x4 |
_ECCP1CON_DC1B_POSITION | none | 0x4 |
_ECCP1CON_DC1B_SIZE | none | 0x2 |
_ECCP1CON_DC1B_LENGTH | none | 0x2 |
_ECCP1CON_DC1B_MASK | none | 0x30 |
_ECCP1CON_P1M_POSN | none | 0x6 |
_ECCP1CON_P1M_POSITION | none | 0x6 |
_ECCP1CON_P1M_SIZE | none | 0x2 |
_ECCP1CON_P1M_LENGTH | none | 0x2 |
_ECCP1CON_P1M_MASK | none | 0xC0 |
_ECCP1CON_CCP1M0_POSN | none | 0x0 |
_ECCP1CON_CCP1M0_POSITION | none | 0x0 |
_ECCP1CON_CCP1M0_SIZE | none | 0x1 |
_ECCP1CON_CCP1M0_LENGTH | none | 0x1 |
_ECCP1CON_CCP1M0_MASK | none | 0x1 |
_ECCP1CON_CCP1M1_POSN | none | 0x1 |
_ECCP1CON_CCP1M1_POSITION | none | 0x1 |
_ECCP1CON_CCP1M1_SIZE | none | 0x1 |
_ECCP1CON_CCP1M1_LENGTH | none | 0x1 |
_ECCP1CON_CCP1M1_MASK | none | 0x2 |
_ECCP1CON_CCP1M2_POSN | none | 0x2 |
_ECCP1CON_CCP1M2_POSITION | none | 0x2 |
_ECCP1CON_CCP1M2_SIZE | none | 0x1 |
_ECCP1CON_CCP1M2_LENGTH | none | 0x1 |
_ECCP1CON_CCP1M2_MASK | none | 0x4 |
_ECCP1CON_CCP1M3_POSN | none | 0x3 |
_ECCP1CON_CCP1M3_POSITION | none | 0x3 |
_ECCP1CON_CCP1M3_SIZE | none | 0x1 |
_ECCP1CON_CCP1M3_LENGTH | none | 0x1 |
_ECCP1CON_CCP1M3_MASK | none | 0x8 |
_ECCP1CON_DC1B0_POSN | none | 0x4 |
_ECCP1CON_DC1B0_POSITION | none | 0x4 |
_ECCP1CON_DC1B0_SIZE | none | 0x1 |
_ECCP1CON_DC1B0_LENGTH | none | 0x1 |
_ECCP1CON_DC1B0_MASK | none | 0x10 |
_ECCP1CON_DC1B1_POSN | none | 0x5 |
_ECCP1CON_DC1B1_POSITION | none | 0x5 |
_ECCP1CON_DC1B1_SIZE | none | 0x1 |
_ECCP1CON_DC1B1_LENGTH | none | 0x1 |
_ECCP1CON_DC1B1_MASK | none | 0x20 |
_ECCP1CON_P1M0_POSN | none | 0x6 |
_ECCP1CON_P1M0_POSITION | none | 0x6 |
_ECCP1CON_P1M0_SIZE | none | 0x1 |
_ECCP1CON_P1M0_LENGTH | none | 0x1 |
_ECCP1CON_P1M0_MASK | none | 0x40 |
_ECCP1CON_P1M1_POSN | none | 0x7 |
_ECCP1CON_P1M1_POSITION | none | 0x7 |
_ECCP1CON_P1M1_SIZE | none | 0x1 |
_ECCP1CON_P1M1_LENGTH | none | 0x1 |
_ECCP1CON_P1M1_MASK | none | 0x80 |
_ADCON2_ADCS_POSN | none | 0x0 |
_ADCON2_ADCS_POSITION | none | 0x0 |
_ADCON2_ADCS_SIZE | none | 0x3 |
_ADCON2_ADCS_LENGTH | none | 0x3 |
_ADCON2_ADCS_MASK | none | 0x7 |
_ADCON2_ACQT_POSN | none | 0x3 |
_ADCON2_ACQT_POSITION | none | 0x3 |
_ADCON2_ACQT_SIZE | none | 0x3 |
_ADCON2_ACQT_LENGTH | none | 0x3 |
_ADCON2_ACQT_MASK | none | 0x38 |
_ADCON2_ADFM_POSN | none | 0x7 |
_ADCON2_ADFM_POSITION | none | 0x7 |
_ADCON2_ADFM_SIZE | none | 0x1 |
_ADCON2_ADFM_LENGTH | none | 0x1 |
_ADCON2_ADFM_MASK | none | 0x80 |
_ADCON2_ADCS0_POSN | none | 0x0 |
_ADCON2_ADCS0_POSITION | none | 0x0 |
_ADCON2_ADCS0_SIZE | none | 0x1 |
_ADCON2_ADCS0_LENGTH | none | 0x1 |
_ADCON2_ADCS0_MASK | none | 0x1 |
_ADCON2_ADCS1_POSN | none | 0x1 |
_ADCON2_ADCS1_POSITION | none | 0x1 |
_ADCON2_ADCS1_SIZE | none | 0x1 |
_ADCON2_ADCS1_LENGTH | none | 0x1 |
_ADCON2_ADCS1_MASK | none | 0x2 |
_ADCON2_ADCS2_POSN | none | 0x2 |
_ADCON2_ADCS2_POSITION | none | 0x2 |
_ADCON2_ADCS2_SIZE | none | 0x1 |
_ADCON2_ADCS2_LENGTH | none | 0x1 |
_ADCON2_ADCS2_MASK | none | 0x4 |
_ADCON2_ACQT0_POSN | none | 0x3 |
_ADCON2_ACQT0_POSITION | none | 0x3 |
_ADCON2_ACQT0_SIZE | none | 0x1 |
_ADCON2_ACQT0_LENGTH | none | 0x1 |
_ADCON2_ACQT0_MASK | none | 0x8 |
_ADCON2_ACQT1_POSN | none | 0x4 |
_ADCON2_ACQT1_POSITION | none | 0x4 |
_ADCON2_ACQT1_SIZE | none | 0x1 |
_ADCON2_ACQT1_LENGTH | none | 0x1 |
_ADCON2_ACQT1_MASK | none | 0x10 |
_ADCON2_ACQT2_POSN | none | 0x5 |
_ADCON2_ACQT2_POSITION | none | 0x5 |
_ADCON2_ACQT2_SIZE | none | 0x1 |
_ADCON2_ACQT2_LENGTH | none | 0x1 |
_ADCON2_ACQT2_MASK | none | 0x20 |
_ADCON1_PCFG_POSN | none | 0x0 |
_ADCON1_PCFG_POSITION | none | 0x0 |
_ADCON1_PCFG_SIZE | none | 0x4 |
_ADCON1_PCFG_LENGTH | none | 0x4 |
_ADCON1_PCFG_MASK | none | 0xF |
_ADCON1_VCFG_POSN | none | 0x4 |
_ADCON1_VCFG_POSITION | none | 0x4 |
_ADCON1_VCFG_SIZE | none | 0x2 |
_ADCON1_VCFG_LENGTH | none | 0x2 |
_ADCON1_VCFG_MASK | none | 0x30 |
_ADCON1_PCFG0_POSN | none | 0x0 |
_ADCON1_PCFG0_POSITION | none | 0x0 |
_ADCON1_PCFG0_SIZE | none | 0x1 |
_ADCON1_PCFG0_LENGTH | none | 0x1 |
_ADCON1_PCFG0_MASK | none | 0x1 |
_ADCON1_PCFG1_POSN | none | 0x1 |
_ADCON1_PCFG1_POSITION | none | 0x1 |
_ADCON1_PCFG1_SIZE | none | 0x1 |
_ADCON1_PCFG1_LENGTH | none | 0x1 |
_ADCON1_PCFG1_MASK | none | 0x2 |
_ADCON1_PCFG2_POSN | none | 0x2 |
_ADCON1_PCFG2_POSITION | none | 0x2 |
_ADCON1_PCFG2_SIZE | none | 0x1 |
_ADCON1_PCFG2_LENGTH | none | 0x1 |
_ADCON1_PCFG2_MASK | none | 0x4 |
_ADCON1_PCFG3_POSN | none | 0x3 |
_ADCON1_PCFG3_POSITION | none | 0x3 |
_ADCON1_PCFG3_SIZE | none | 0x1 |
_ADCON1_PCFG3_LENGTH | none | 0x1 |
_ADCON1_PCFG3_MASK | none | 0x8 |
_ADCON1_VCFG0_POSN | none | 0x4 |
_ADCON1_VCFG0_POSITION | none | 0x4 |
_ADCON1_VCFG0_SIZE | none | 0x1 |
_ADCON1_VCFG0_LENGTH | none | 0x1 |
_ADCON1_VCFG0_MASK | none | 0x10 |
_ADCON1_VCFG1_POSN | none | 0x5 |
_ADCON1_VCFG1_POSITION | none | 0x5 |
_ADCON1_VCFG1_SIZE | none | 0x1 |
_ADCON1_VCFG1_LENGTH | none | 0x1 |
_ADCON1_VCFG1_MASK | none | 0x20 |
_ADCON1_CHSN3_POSN | none | 0x3 |
_ADCON1_CHSN3_POSITION | none | 0x3 |
_ADCON1_CHSN3_SIZE | none | 0x1 |
_ADCON1_CHSN3_LENGTH | none | 0x1 |
_ADCON1_CHSN3_MASK | none | 0x8 |
_ADCON1_VCFG01_POSN | none | 0x4 |
_ADCON1_VCFG01_POSITION | none | 0x4 |
_ADCON1_VCFG01_SIZE | none | 0x1 |
_ADCON1_VCFG01_LENGTH | none | 0x1 |
_ADCON1_VCFG01_MASK | none | 0x10 |
_ADCON1_VCFG11_POSN | none | 0x5 |
_ADCON1_VCFG11_POSITION | none | 0x5 |
_ADCON1_VCFG11_SIZE | none | 0x1 |
_ADCON1_VCFG11_LENGTH | none | 0x1 |
_ADCON1_VCFG11_MASK | none | 0x20 |
_ADCON0_GO_NOT_DONE_POSN | none | 0x1 |
_ADCON0_GO_NOT_DONE_POSITION | none | 0x1 |
_ADCON0_GO_NOT_DONE_SIZE | none | 0x1 |
_ADCON0_GO_NOT_DONE_LENGTH | none | 0x1 |
_ADCON0_GO_NOT_DONE_MASK | none | 0x2 |
_ADCON0_ADON_POSN | none | 0x0 |
_ADCON0_ADON_POSITION | none | 0x0 |
_ADCON0_ADON_SIZE | none | 0x1 |
_ADCON0_ADON_LENGTH | none | 0x1 |
_ADCON0_ADON_MASK | none | 0x1 |
_ADCON0_GO_nDONE_POSN | none | 0x1 |
_ADCON0_GO_nDONE_POSITION | none | 0x1 |
_ADCON0_GO_nDONE_SIZE | none | 0x1 |
_ADCON0_GO_nDONE_LENGTH | none | 0x1 |
_ADCON0_GO_nDONE_MASK | none | 0x2 |
_ADCON0_CHS_POSN | none | 0x2 |
_ADCON0_CHS_POSITION | none | 0x2 |
_ADCON0_CHS_SIZE | none | 0x4 |
_ADCON0_CHS_LENGTH | none | 0x4 |
_ADCON0_CHS_MASK | none | 0x3C |
_ADCON0_GO_DONE_POSN | none | 0x1 |
_ADCON0_GO_DONE_POSITION | none | 0x1 |
_ADCON0_GO_DONE_SIZE | none | 0x1 |
_ADCON0_GO_DONE_LENGTH | none | 0x1 |
_ADCON0_GO_DONE_MASK | none | 0x2 |
_ADCON0_CHS0_POSN | none | 0x2 |
_ADCON0_CHS0_POSITION | none | 0x2 |
_ADCON0_CHS0_SIZE | none | 0x1 |
_ADCON0_CHS0_LENGTH | none | 0x1 |
_ADCON0_CHS0_MASK | none | 0x4 |
_ADCON0_CHS1_POSN | none | 0x3 |
_ADCON0_CHS1_POSITION | none | 0x3 |
_ADCON0_CHS1_SIZE | none | 0x1 |
_ADCON0_CHS1_LENGTH | none | 0x1 |
_ADCON0_CHS1_MASK | none | 0x8 |
_ADCON0_CHS2_POSN | none | 0x4 |
_ADCON0_CHS2_POSITION | none | 0x4 |
_ADCON0_CHS2_SIZE | none | 0x1 |
_ADCON0_CHS2_LENGTH | none | 0x1 |
_ADCON0_CHS2_MASK | none | 0x10 |
_ADCON0_CHS3_POSN | none | 0x5 |
_ADCON0_CHS3_POSITION | none | 0x5 |
_ADCON0_CHS3_SIZE | none | 0x1 |
_ADCON0_CHS3_LENGTH | none | 0x1 |
_ADCON0_CHS3_MASK | none | 0x20 |
_ADCON0_DONE_POSN | none | 0x1 |
_ADCON0_DONE_POSITION | none | 0x1 |
_ADCON0_DONE_SIZE | none | 0x1 |
_ADCON0_DONE_LENGTH | none | 0x1 |
_ADCON0_DONE_MASK | none | 0x2 |
_ADCON0_GO_POSN | none | 0x1 |
_ADCON0_GO_POSITION | none | 0x1 |
_ADCON0_GO_SIZE | none | 0x1 |
_ADCON0_GO_LENGTH | none | 0x1 |
_ADCON0_GO_MASK | none | 0x2 |
_ADCON0_NOT_DONE_POSN | none | 0x1 |
_ADCON0_NOT_DONE_POSITION | none | 0x1 |
_ADCON0_NOT_DONE_SIZE | none | 0x1 |
_ADCON0_NOT_DONE_LENGTH | none | 0x1 |
_ADCON0_NOT_DONE_MASK | none | 0x2 |
_ADCON0_nDONE_POSN | none | 0x1 |
_ADCON0_nDONE_POSITION | none | 0x1 |
_ADCON0_nDONE_SIZE | none | 0x1 |
_ADCON0_nDONE_LENGTH | none | 0x1 |
_ADCON0_nDONE_MASK | none | 0x2 |
_ADCON0_GODONE_POSN | none | 0x1 |
_ADCON0_GODONE_POSITION | none | 0x1 |
_ADCON0_GODONE_SIZE | none | 0x1 |
_ADCON0_GODONE_LENGTH | none | 0x1 |
_ADCON0_GODONE_MASK | none | 0x2 |
_SSPCON2_SEN_POSN | none | 0x0 |
_SSPCON2_SEN_POSITION | none | 0x0 |
_SSPCON2_SEN_SIZE | none | 0x1 |
_SSPCON2_SEN_LENGTH | none | 0x1 |
_SSPCON2_SEN_MASK | none | 0x1 |
_SSPCON2_RSEN_POSN | none | 0x1 |
_SSPCON2_RSEN_POSITION | none | 0x1 |
_SSPCON2_RSEN_SIZE | none | 0x1 |
_SSPCON2_RSEN_LENGTH | none | 0x1 |
_SSPCON2_RSEN_MASK | none | 0x2 |
_SSPCON2_PEN_POSN | none | 0x2 |
_SSPCON2_PEN_POSITION | none | 0x2 |
_SSPCON2_PEN_SIZE | none | 0x1 |
_SSPCON2_PEN_LENGTH | none | 0x1 |
_SSPCON2_PEN_MASK | none | 0x4 |
_SSPCON2_RCEN_POSN | none | 0x3 |
_SSPCON2_RCEN_POSITION | none | 0x3 |
_SSPCON2_RCEN_SIZE | none | 0x1 |
_SSPCON2_RCEN_LENGTH | none | 0x1 |
_SSPCON2_RCEN_MASK | none | 0x8 |
_SSPCON2_ACKEN_POSN | none | 0x4 |
_SSPCON2_ACKEN_POSITION | none | 0x4 |
_SSPCON2_ACKEN_SIZE | none | 0x1 |
_SSPCON2_ACKEN_LENGTH | none | 0x1 |
_SSPCON2_ACKEN_MASK | none | 0x10 |
_SSPCON2_ACKDT_POSN | none | 0x5 |
_SSPCON2_ACKDT_POSITION | none | 0x5 |
_SSPCON2_ACKDT_SIZE | none | 0x1 |
_SSPCON2_ACKDT_LENGTH | none | 0x1 |
_SSPCON2_ACKDT_MASK | none | 0x20 |
_SSPCON2_ACKSTAT_POSN | none | 0x6 |
_SSPCON2_ACKSTAT_POSITION | none | 0x6 |
_SSPCON2_ACKSTAT_SIZE | none | 0x1 |
_SSPCON2_ACKSTAT_LENGTH | none | 0x1 |
_SSPCON2_ACKSTAT_MASK | none | 0x40 |
_SSPCON2_GCEN_POSN | none | 0x7 |
_SSPCON2_GCEN_POSITION | none | 0x7 |
_SSPCON2_GCEN_SIZE | none | 0x1 |
_SSPCON2_GCEN_LENGTH | none | 0x1 |
_SSPCON2_GCEN_MASK | none | 0x80 |
_SSPCON1_SSPM_POSN | none | 0x0 |
_SSPCON1_SSPM_POSITION | none | 0x0 |
_SSPCON1_SSPM_SIZE | none | 0x4 |
_SSPCON1_SSPM_LENGTH | none | 0x4 |
_SSPCON1_SSPM_MASK | none | 0xF |
_SSPCON1_CKP_POSN | none | 0x4 |
_SSPCON1_CKP_POSITION | none | 0x4 |
_SSPCON1_CKP_SIZE | none | 0x1 |
_SSPCON1_CKP_LENGTH | none | 0x1 |
_SSPCON1_CKP_MASK | none | 0x10 |
_SSPCON1_SSPEN_POSN | none | 0x5 |
_SSPCON1_SSPEN_POSITION | none | 0x5 |
_SSPCON1_SSPEN_SIZE | none | 0x1 |
_SSPCON1_SSPEN_LENGTH | none | 0x1 |
_SSPCON1_SSPEN_MASK | none | 0x20 |
_SSPCON1_SSPOV_POSN | none | 0x6 |
_SSPCON1_SSPOV_POSITION | none | 0x6 |
_SSPCON1_SSPOV_SIZE | none | 0x1 |
_SSPCON1_SSPOV_LENGTH | none | 0x1 |
_SSPCON1_SSPOV_MASK | none | 0x40 |
_SSPCON1_WCOL_POSN | none | 0x7 |
_SSPCON1_WCOL_POSITION | none | 0x7 |
_SSPCON1_WCOL_SIZE | none | 0x1 |
_SSPCON1_WCOL_LENGTH | none | 0x1 |
_SSPCON1_WCOL_MASK | none | 0x80 |
_SSPCON1_SSPM0_POSN | none | 0x0 |
_SSPCON1_SSPM0_POSITION | none | 0x0 |
_SSPCON1_SSPM0_SIZE | none | 0x1 |
_SSPCON1_SSPM0_LENGTH | none | 0x1 |
_SSPCON1_SSPM0_MASK | none | 0x1 |
_SSPCON1_SSPM1_POSN | none | 0x1 |
_SSPCON1_SSPM1_POSITION | none | 0x1 |
_SSPCON1_SSPM1_SIZE | none | 0x1 |
_SSPCON1_SSPM1_LENGTH | none | 0x1 |
_SSPCON1_SSPM1_MASK | none | 0x2 |
_SSPCON1_SSPM2_POSN | none | 0x2 |
_SSPCON1_SSPM2_POSITION | none | 0x2 |
_SSPCON1_SSPM2_SIZE | none | 0x1 |
_SSPCON1_SSPM2_LENGTH | none | 0x1 |
_SSPCON1_SSPM2_MASK | none | 0x4 |
_SSPCON1_SSPM3_POSN | none | 0x3 |
_SSPCON1_SSPM3_POSITION | none | 0x3 |
_SSPCON1_SSPM3_SIZE | none | 0x1 |
_SSPCON1_SSPM3_LENGTH | none | 0x1 |
_SSPCON1_SSPM3_MASK | none | 0x8 |
_SSPSTAT_R_NOT_W_POSN | none | 0x2 |
_SSPSTAT_R_NOT_W_POSITION | none | 0x2 |
_SSPSTAT_R_NOT_W_SIZE | none | 0x1 |
_SSPSTAT_R_NOT_W_LENGTH | none | 0x1 |
_SSPSTAT_R_NOT_W_MASK | none | 0x4 |
_SSPSTAT_D_NOT_A_POSN | none | 0x5 |
_SSPSTAT_D_NOT_A_POSITION | none | 0x5 |
_SSPSTAT_D_NOT_A_SIZE | none | 0x1 |
_SSPSTAT_D_NOT_A_LENGTH | none | 0x1 |
_SSPSTAT_D_NOT_A_MASK | none | 0x20 |
_SSPSTAT_BF_POSN | none | 0x0 |
_SSPSTAT_BF_POSITION | none | 0x0 |
_SSPSTAT_BF_SIZE | none | 0x1 |
_SSPSTAT_BF_LENGTH | none | 0x1 |
_SSPSTAT_BF_MASK | none | 0x1 |
_SSPSTAT_UA_POSN | none | 0x1 |
_SSPSTAT_UA_POSITION | none | 0x1 |
_SSPSTAT_UA_SIZE | none | 0x1 |
_SSPSTAT_UA_LENGTH | none | 0x1 |
_SSPSTAT_UA_MASK | none | 0x2 |
_SSPSTAT_R_nW_POSN | none | 0x2 |
_SSPSTAT_R_nW_POSITION | none | 0x2 |
_SSPSTAT_R_nW_SIZE | none | 0x1 |
_SSPSTAT_R_nW_LENGTH | none | 0x1 |
_SSPSTAT_R_nW_MASK | none | 0x4 |
_SSPSTAT_S_POSN | none | 0x3 |
_SSPSTAT_S_POSITION | none | 0x3 |
_SSPSTAT_S_SIZE | none | 0x1 |
_SSPSTAT_S_LENGTH | none | 0x1 |
_SSPSTAT_S_MASK | none | 0x8 |
_SSPSTAT_P_POSN | none | 0x4 |
_SSPSTAT_P_POSITION | none | 0x4 |
_SSPSTAT_P_SIZE | none | 0x1 |
_SSPSTAT_P_LENGTH | none | 0x1 |
_SSPSTAT_P_MASK | none | 0x10 |
_SSPSTAT_D_nA_POSN | none | 0x5 |
_SSPSTAT_D_nA_POSITION | none | 0x5 |
_SSPSTAT_D_nA_SIZE | none | 0x1 |
_SSPSTAT_D_nA_LENGTH | none | 0x1 |
_SSPSTAT_D_nA_MASK | none | 0x20 |
_SSPSTAT_CKE_POSN | none | 0x6 |
_SSPSTAT_CKE_POSITION | none | 0x6 |
_SSPSTAT_CKE_SIZE | none | 0x1 |
_SSPSTAT_CKE_LENGTH | none | 0x1 |
_SSPSTAT_CKE_MASK | none | 0x40 |
_SSPSTAT_SMP_POSN | none | 0x7 |
_SSPSTAT_SMP_POSITION | none | 0x7 |
_SSPSTAT_SMP_SIZE | none | 0x1 |
_SSPSTAT_SMP_LENGTH | none | 0x1 |
_SSPSTAT_SMP_MASK | none | 0x80 |
_SSPSTAT_R_W_POSN | none | 0x2 |
_SSPSTAT_R_W_POSITION | none | 0x2 |
_SSPSTAT_R_W_SIZE | none | 0x1 |
_SSPSTAT_R_W_LENGTH | none | 0x1 |
_SSPSTAT_R_W_MASK | none | 0x4 |
_SSPSTAT_D_A_POSN | none | 0x5 |
_SSPSTAT_D_A_POSITION | none | 0x5 |
_SSPSTAT_D_A_SIZE | none | 0x1 |
_SSPSTAT_D_A_LENGTH | none | 0x1 |
_SSPSTAT_D_A_MASK | none | 0x20 |
_SSPSTAT_I2C_READ_POSN | none | 0x2 |
_SSPSTAT_I2C_READ_POSITION | none | 0x2 |
_SSPSTAT_I2C_READ_SIZE | none | 0x1 |
_SSPSTAT_I2C_READ_LENGTH | none | 0x1 |
_SSPSTAT_I2C_READ_MASK | none | 0x4 |
_SSPSTAT_I2C_START_POSN | none | 0x3 |
_SSPSTAT_I2C_START_POSITION | none | 0x3 |
_SSPSTAT_I2C_START_SIZE | none | 0x1 |
_SSPSTAT_I2C_START_LENGTH | none | 0x1 |
_SSPSTAT_I2C_START_MASK | none | 0x8 |
_SSPSTAT_I2C_STOP_POSN | none | 0x4 |
_SSPSTAT_I2C_STOP_POSITION | none | 0x4 |
_SSPSTAT_I2C_STOP_SIZE | none | 0x1 |
_SSPSTAT_I2C_STOP_LENGTH | none | 0x1 |
_SSPSTAT_I2C_STOP_MASK | none | 0x10 |
_SSPSTAT_I2C_DAT_POSN | none | 0x5 |
_SSPSTAT_I2C_DAT_POSITION | none | 0x5 |
_SSPSTAT_I2C_DAT_SIZE | none | 0x1 |
_SSPSTAT_I2C_DAT_LENGTH | none | 0x1 |
_SSPSTAT_I2C_DAT_MASK | none | 0x20 |
_SSPSTAT_nW_POSN | none | 0x2 |
_SSPSTAT_nW_POSITION | none | 0x2 |
_SSPSTAT_nW_SIZE | none | 0x1 |
_SSPSTAT_nW_LENGTH | none | 0x1 |
_SSPSTAT_nW_MASK | none | 0x4 |
_SSPSTAT_nA_POSN | none | 0x5 |
_SSPSTAT_nA_POSITION | none | 0x5 |
_SSPSTAT_nA_SIZE | none | 0x1 |
_SSPSTAT_nA_LENGTH | none | 0x1 |
_SSPSTAT_nA_MASK | none | 0x20 |
_SSPSTAT_NOT_WRITE_POSN | none | 0x2 |
_SSPSTAT_NOT_WRITE_POSITION | none | 0x2 |
_SSPSTAT_NOT_WRITE_SIZE | none | 0x1 |
_SSPSTAT_NOT_WRITE_LENGTH | none | 0x1 |
_SSPSTAT_NOT_WRITE_MASK | none | 0x4 |
_SSPSTAT_NOT_ADDRESS_POSN | none | 0x5 |
_SSPSTAT_NOT_ADDRESS_POSITION | none | 0x5 |
_SSPSTAT_NOT_ADDRESS_SIZE | none | 0x1 |
_SSPSTAT_NOT_ADDRESS_LENGTH | none | 0x1 |
_SSPSTAT_NOT_ADDRESS_MASK | none | 0x20 |
_SSPSTAT_nWRITE_POSN | none | 0x2 |
_SSPSTAT_nWRITE_POSITION | none | 0x2 |
_SSPSTAT_nWRITE_SIZE | none | 0x1 |
_SSPSTAT_nWRITE_LENGTH | none | 0x1 |
_SSPSTAT_nWRITE_MASK | none | 0x4 |
_SSPSTAT_nADDRESS_POSN | none | 0x5 |
_SSPSTAT_nADDRESS_POSITION | none | 0x5 |
_SSPSTAT_nADDRESS_SIZE | none | 0x1 |
_SSPSTAT_nADDRESS_LENGTH | none | 0x1 |
_SSPSTAT_nADDRESS_MASK | none | 0x20 |
_SSPSTAT_READ_WRITE_POSN | none | 0x2 |
_SSPSTAT_READ_WRITE_POSITION | none | 0x2 |
_SSPSTAT_READ_WRITE_SIZE | none | 0x1 |
_SSPSTAT_READ_WRITE_LENGTH | none | 0x1 |
_SSPSTAT_READ_WRITE_MASK | none | 0x4 |
_SSPSTAT_DATA_ADDRESS_POSN | none | 0x5 |
_SSPSTAT_DATA_ADDRESS_POSITION | none | 0x5 |
_SSPSTAT_DATA_ADDRESS_SIZE | none | 0x1 |
_SSPSTAT_DATA_ADDRESS_LENGTH | none | 0x1 |
_SSPSTAT_DATA_ADDRESS_MASK | none | 0x20 |
_SSPSTAT_R_POSN | none | 0x2 |
_SSPSTAT_R_POSITION | none | 0x2 |
_SSPSTAT_R_SIZE | none | 0x1 |
_SSPSTAT_R_LENGTH | none | 0x1 |
_SSPSTAT_R_MASK | none | 0x4 |
_SSPSTAT_D_POSN | none | 0x5 |
_SSPSTAT_D_POSITION | none | 0x5 |
_SSPSTAT_D_SIZE | none | 0x1 |
_SSPSTAT_D_LENGTH | none | 0x1 |
_SSPSTAT_D_MASK | none | 0x20 |
_SSPSTAT_DA_POSN | none | 0x5 |
_SSPSTAT_DA_POSITION | none | 0x5 |
_SSPSTAT_DA_SIZE | none | 0x1 |
_SSPSTAT_DA_LENGTH | none | 0x1 |
_SSPSTAT_DA_MASK | none | 0x20 |
_SSPSTAT_RW_POSN | none | 0x2 |
_SSPSTAT_RW_POSITION | none | 0x2 |
_SSPSTAT_RW_SIZE | none | 0x1 |
_SSPSTAT_RW_LENGTH | none | 0x1 |
_SSPSTAT_RW_MASK | none | 0x4 |
_SSPSTAT_START_POSN | none | 0x3 |
_SSPSTAT_START_POSITION | none | 0x3 |
_SSPSTAT_START_SIZE | none | 0x1 |
_SSPSTAT_START_LENGTH | none | 0x1 |
_SSPSTAT_START_MASK | none | 0x8 |
_SSPSTAT_STOP_POSN | none | 0x4 |
_SSPSTAT_STOP_POSITION | none | 0x4 |
_SSPSTAT_STOP_SIZE | none | 0x1 |
_SSPSTAT_STOP_LENGTH | none | 0x1 |
_SSPSTAT_STOP_MASK | none | 0x10 |
_SSPSTAT_NOT_W_POSN | none | 0x2 |
_SSPSTAT_NOT_W_POSITION | none | 0x2 |
_SSPSTAT_NOT_W_SIZE | none | 0x1 |
_SSPSTAT_NOT_W_LENGTH | none | 0x1 |
_SSPSTAT_NOT_W_MASK | none | 0x4 |
_SSPSTAT_NOT_A_POSN | none | 0x5 |
_SSPSTAT_NOT_A_POSITION | none | 0x5 |
_SSPSTAT_NOT_A_SIZE | none | 0x1 |
_SSPSTAT_NOT_A_LENGTH | none | 0x1 |
_SSPSTAT_NOT_A_MASK | none | 0x20 |
_T2CON_T2CKPS_POSN | none | 0x0 |
_T2CON_T2CKPS_POSITION | none | 0x0 |
_T2CON_T2CKPS_SIZE | none | 0x2 |
_T2CON_T2CKPS_LENGTH | none | 0x2 |
_T2CON_T2CKPS_MASK | none | 0x3 |
_T2CON_TMR2ON_POSN | none | 0x2 |
_T2CON_TMR2ON_POSITION | none | 0x2 |
_T2CON_TMR2ON_SIZE | none | 0x1 |
_T2CON_TMR2ON_LENGTH | none | 0x1 |
_T2CON_TMR2ON_MASK | none | 0x4 |
_T2CON_TOUTPS_POSN | none | 0x3 |
_T2CON_TOUTPS_POSITION | none | 0x3 |
_T2CON_TOUTPS_SIZE | none | 0x4 |
_T2CON_TOUTPS_LENGTH | none | 0x4 |
_T2CON_TOUTPS_MASK | none | 0x78 |
_T2CON_T2CKPS0_POSN | none | 0x0 |
_T2CON_T2CKPS0_POSITION | none | 0x0 |
_T2CON_T2CKPS0_SIZE | none | 0x1 |
_T2CON_T2CKPS0_LENGTH | none | 0x1 |
_T2CON_T2CKPS0_MASK | none | 0x1 |
_T2CON_T2CKPS1_POSN | none | 0x1 |
_T2CON_T2CKPS1_POSITION | none | 0x1 |
_T2CON_T2CKPS1_SIZE | none | 0x1 |
_T2CON_T2CKPS1_LENGTH | none | 0x1 |
_T2CON_T2CKPS1_MASK | none | 0x2 |
_T2CON_T2OUTPS0_POSN | none | 0x3 |
_T2CON_T2OUTPS0_POSITION | none | 0x3 |
_T2CON_T2OUTPS0_SIZE | none | 0x1 |
_T2CON_T2OUTPS0_LENGTH | none | 0x1 |
_T2CON_T2OUTPS0_MASK | none | 0x8 |
_T2CON_T2OUTPS1_POSN | none | 0x4 |
_T2CON_T2OUTPS1_POSITION | none | 0x4 |
_T2CON_T2OUTPS1_SIZE | none | 0x1 |
_T2CON_T2OUTPS1_LENGTH | none | 0x1 |
_T2CON_T2OUTPS1_MASK | none | 0x10 |
_T2CON_T2OUTPS2_POSN | none | 0x5 |
_T2CON_T2OUTPS2_POSITION | none | 0x5 |
_T2CON_T2OUTPS2_SIZE | none | 0x1 |
_T2CON_T2OUTPS2_LENGTH | none | 0x1 |
_T2CON_T2OUTPS2_MASK | none | 0x20 |
_T2CON_T2OUTPS3_POSN | none | 0x6 |
_T2CON_T2OUTPS3_POSITION | none | 0x6 |
_T2CON_T2OUTPS3_SIZE | none | 0x1 |
_T2CON_T2OUTPS3_LENGTH | none | 0x1 |
_T2CON_T2OUTPS3_MASK | none | 0x40 |
_T2CON_TOUTPS0_POSN | none | 0x3 |
_T2CON_TOUTPS0_POSITION | none | 0x3 |
_T2CON_TOUTPS0_SIZE | none | 0x1 |
_T2CON_TOUTPS0_LENGTH | none | 0x1 |
_T2CON_TOUTPS0_MASK | none | 0x8 |
_T2CON_TOUTPS1_POSN | none | 0x4 |
_T2CON_TOUTPS1_POSITION | none | 0x4 |
_T2CON_TOUTPS1_SIZE | none | 0x1 |
_T2CON_TOUTPS1_LENGTH | none | 0x1 |
_T2CON_TOUTPS1_MASK | none | 0x10 |
_T2CON_TOUTPS2_POSN | none | 0x5 |
_T2CON_TOUTPS2_POSITION | none | 0x5 |
_T2CON_TOUTPS2_SIZE | none | 0x1 |
_T2CON_TOUTPS2_LENGTH | none | 0x1 |
_T2CON_TOUTPS2_MASK | none | 0x20 |
_T2CON_TOUTPS3_POSN | none | 0x6 |
_T2CON_TOUTPS3_POSITION | none | 0x6 |
_T2CON_TOUTPS3_SIZE | none | 0x1 |
_T2CON_TOUTPS3_LENGTH | none | 0x1 |
_T2CON_TOUTPS3_MASK | none | 0x40 |
_PR2_EBDIS_POSN | none | 0x7 |
_PR2_EBDIS_POSITION | none | 0x7 |
_PR2_EBDIS_SIZE | none | 0x1 |
_PR2_EBDIS_LENGTH | none | 0x1 |
_PR2_EBDIS_MASK | none | 0x80 |
_PR2_WAIT0_POSN | none | 0x4 |
_PR2_WAIT0_POSITION | none | 0x4 |
_PR2_WAIT0_SIZE | none | 0x1 |
_PR2_WAIT0_LENGTH | none | 0x1 |
_PR2_WAIT0_MASK | none | 0x10 |
_PR2_WAIT1_POSN | none | 0x5 |
_PR2_WAIT1_POSITION | none | 0x5 |
_PR2_WAIT1_SIZE | none | 0x1 |
_PR2_WAIT1_LENGTH | none | 0x1 |
_PR2_WAIT1_MASK | none | 0x20 |
_PR2_WM0_POSN | none | 0x0 |
_PR2_WM0_POSITION | none | 0x0 |
_PR2_WM0_SIZE | none | 0x1 |
_PR2_WM0_LENGTH | none | 0x1 |
_PR2_WM0_MASK | none | 0x1 |
_PR2_WM1_POSN | none | 0x1 |
_PR2_WM1_POSITION | none | 0x1 |
_PR2_WM1_SIZE | none | 0x1 |
_PR2_WM1_LENGTH | none | 0x1 |
_PR2_WM1_MASK | none | 0x2 |
_MEMCON_EBDIS_POSN | none | 0x7 |
_MEMCON_EBDIS_POSITION | none | 0x7 |
_MEMCON_EBDIS_SIZE | none | 0x1 |
_MEMCON_EBDIS_LENGTH | none | 0x1 |
_MEMCON_EBDIS_MASK | none | 0x80 |
_MEMCON_WAIT0_POSN | none | 0x4 |
_MEMCON_WAIT0_POSITION | none | 0x4 |
_MEMCON_WAIT0_SIZE | none | 0x1 |
_MEMCON_WAIT0_LENGTH | none | 0x1 |
_MEMCON_WAIT0_MASK | none | 0x10 |
_MEMCON_WAIT1_POSN | none | 0x5 |
_MEMCON_WAIT1_POSITION | none | 0x5 |
_MEMCON_WAIT1_SIZE | none | 0x1 |
_MEMCON_WAIT1_LENGTH | none | 0x1 |
_MEMCON_WAIT1_MASK | none | 0x20 |
_MEMCON_WM0_POSN | none | 0x0 |
_MEMCON_WM0_POSITION | none | 0x0 |
_MEMCON_WM0_SIZE | none | 0x1 |
_MEMCON_WM0_LENGTH | none | 0x1 |
_MEMCON_WM0_MASK | none | 0x1 |
_MEMCON_WM1_POSN | none | 0x1 |
_MEMCON_WM1_POSITION | none | 0x1 |
_MEMCON_WM1_SIZE | none | 0x1 |
_MEMCON_WM1_LENGTH | none | 0x1 |
_MEMCON_WM1_MASK | none | 0x2 |
_T1CON_NOT_T1SYNC_POSN | none | 0x2 |
_T1CON_NOT_T1SYNC_POSITION | none | 0x2 |
_T1CON_NOT_T1SYNC_SIZE | none | 0x1 |
_T1CON_NOT_T1SYNC_LENGTH | none | 0x1 |
_T1CON_NOT_T1SYNC_MASK | none | 0x4 |
_T1CON_TMR1ON_POSN | none | 0x0 |
_T1CON_TMR1ON_POSITION | none | 0x0 |
_T1CON_TMR1ON_SIZE | none | 0x1 |
_T1CON_TMR1ON_LENGTH | none | 0x1 |
_T1CON_TMR1ON_MASK | none | 0x1 |
_T1CON_TMR1CS_POSN | none | 0x1 |
_T1CON_TMR1CS_POSITION | none | 0x1 |
_T1CON_TMR1CS_SIZE | none | 0x1 |
_T1CON_TMR1CS_LENGTH | none | 0x1 |
_T1CON_TMR1CS_MASK | none | 0x2 |
_T1CON_nT1SYNC_POSN | none | 0x2 |
_T1CON_nT1SYNC_POSITION | none | 0x2 |
_T1CON_nT1SYNC_SIZE | none | 0x1 |
_T1CON_nT1SYNC_LENGTH | none | 0x1 |
_T1CON_nT1SYNC_MASK | none | 0x4 |
_T1CON_T1OSCEN_POSN | none | 0x3 |
_T1CON_T1OSCEN_POSITION | none | 0x3 |
_T1CON_T1OSCEN_SIZE | none | 0x1 |
_T1CON_T1OSCEN_LENGTH | none | 0x1 |
_T1CON_T1OSCEN_MASK | none | 0x8 |
_T1CON_T1CKPS_POSN | none | 0x4 |
_T1CON_T1CKPS_POSITION | none | 0x4 |
_T1CON_T1CKPS_SIZE | none | 0x2 |
_T1CON_T1CKPS_LENGTH | none | 0x2 |
_T1CON_T1CKPS_MASK | none | 0x30 |
_T1CON_T1RUN_POSN | none | 0x6 |
_T1CON_T1RUN_POSITION | none | 0x6 |
_T1CON_T1RUN_SIZE | none | 0x1 |
_T1CON_T1RUN_LENGTH | none | 0x1 |
_T1CON_T1RUN_MASK | none | 0x40 |
_T1CON_RD16_POSN | none | 0x7 |
_T1CON_RD16_POSITION | none | 0x7 |
_T1CON_RD16_SIZE | none | 0x1 |
_T1CON_RD16_LENGTH | none | 0x1 |
_T1CON_RD16_MASK | none | 0x80 |
_T1CON_T1SYNC_POSN | none | 0x2 |
_T1CON_T1SYNC_POSITION | none | 0x2 |
_T1CON_T1SYNC_SIZE | none | 0x1 |
_T1CON_T1SYNC_LENGTH | none | 0x1 |
_T1CON_T1SYNC_MASK | none | 0x4 |
_T1CON_T1CKPS0_POSN | none | 0x4 |
_T1CON_T1CKPS0_POSITION | none | 0x4 |
_T1CON_T1CKPS0_SIZE | none | 0x1 |
_T1CON_T1CKPS0_LENGTH | none | 0x1 |
_T1CON_T1CKPS0_MASK | none | 0x10 |
_T1CON_T1CKPS1_POSN | none | 0x5 |
_T1CON_T1CKPS1_POSITION | none | 0x5 |
_T1CON_T1CKPS1_SIZE | none | 0x1 |
_T1CON_T1CKPS1_LENGTH | none | 0x1 |
_T1CON_T1CKPS1_MASK | none | 0x20 |
_T1CON_SOSCEN_POSN | none | 0x3 |
_T1CON_SOSCEN_POSITION | none | 0x3 |
_T1CON_SOSCEN_SIZE | none | 0x1 |
_T1CON_SOSCEN_LENGTH | none | 0x1 |
_T1CON_SOSCEN_MASK | none | 0x8 |
_T1CON_T1RD16_POSN | none | 0x7 |
_T1CON_T1RD16_POSITION | none | 0x7 |
_T1CON_T1RD16_SIZE | none | 0x1 |
_T1CON_T1RD16_LENGTH | none | 0x1 |
_T1CON_T1RD16_MASK | none | 0x80 |
_RCON_NOT_BOR_POSN | none | 0x0 |
_RCON_NOT_BOR_POSITION | none | 0x0 |
_RCON_NOT_BOR_SIZE | none | 0x1 |
_RCON_NOT_BOR_LENGTH | none | 0x1 |
_RCON_NOT_BOR_MASK | none | 0x1 |
_RCON_NOT_POR_POSN | none | 0x1 |
_RCON_NOT_POR_POSITION | none | 0x1 |
_RCON_NOT_POR_SIZE | none | 0x1 |
_RCON_NOT_POR_LENGTH | none | 0x1 |
_RCON_NOT_POR_MASK | none | 0x2 |
_RCON_NOT_PD_POSN | none | 0x2 |
_RCON_NOT_PD_POSITION | none | 0x2 |
_RCON_NOT_PD_SIZE | none | 0x1 |
_RCON_NOT_PD_LENGTH | none | 0x1 |
_RCON_NOT_PD_MASK | none | 0x4 |
_RCON_NOT_TO_POSN | none | 0x3 |
_RCON_NOT_TO_POSITION | none | 0x3 |
_RCON_NOT_TO_SIZE | none | 0x1 |
_RCON_NOT_TO_LENGTH | none | 0x1 |
_RCON_NOT_TO_MASK | none | 0x8 |
_RCON_NOT_RI_POSN | none | 0x4 |
_RCON_NOT_RI_POSITION | none | 0x4 |
_RCON_NOT_RI_SIZE | none | 0x1 |
_RCON_NOT_RI_LENGTH | none | 0x1 |
_RCON_NOT_RI_MASK | none | 0x10 |
_RCON_nBOR_POSN | none | 0x0 |
_RCON_nBOR_POSITION | none | 0x0 |
_RCON_nBOR_SIZE | none | 0x1 |
_RCON_nBOR_LENGTH | none | 0x1 |
_RCON_nBOR_MASK | none | 0x1 |
_RCON_nPOR_POSN | none | 0x1 |
_RCON_nPOR_POSITION | none | 0x1 |
_RCON_nPOR_SIZE | none | 0x1 |
_RCON_nPOR_LENGTH | none | 0x1 |
_RCON_nPOR_MASK | none | 0x2 |
_RCON_nPD_POSN | none | 0x2 |
_RCON_nPD_POSITION | none | 0x2 |
_RCON_nPD_SIZE | none | 0x1 |
_RCON_nPD_LENGTH | none | 0x1 |
_RCON_nPD_MASK | none | 0x4 |
_RCON_nTO_POSN | none | 0x3 |
_RCON_nTO_POSITION | none | 0x3 |
_RCON_nTO_SIZE | none | 0x1 |
_RCON_nTO_LENGTH | none | 0x1 |
_RCON_nTO_MASK | none | 0x8 |
_RCON_nRI_POSN | none | 0x4 |
_RCON_nRI_POSITION | none | 0x4 |
_RCON_nRI_SIZE | none | 0x1 |
_RCON_nRI_LENGTH | none | 0x1 |
_RCON_nRI_MASK | none | 0x10 |
_RCON_SBOREN_POSN | none | 0x6 |
_RCON_SBOREN_POSITION | none | 0x6 |
_RCON_SBOREN_SIZE | none | 0x1 |
_RCON_SBOREN_LENGTH | none | 0x1 |
_RCON_SBOREN_MASK | none | 0x40 |
_RCON_IPEN_POSN | none | 0x7 |
_RCON_IPEN_POSITION | none | 0x7 |
_RCON_IPEN_SIZE | none | 0x1 |
_RCON_IPEN_LENGTH | none | 0x1 |
_RCON_IPEN_MASK | none | 0x80 |
_RCON_NOT_IPEN_POSN | none | 0x7 |
_RCON_NOT_IPEN_POSITION | none | 0x7 |
_RCON_NOT_IPEN_SIZE | none | 0x1 |
_RCON_NOT_IPEN_LENGTH | none | 0x1 |
_RCON_NOT_IPEN_MASK | none | 0x80 |
_RCON_BOR_POSN | none | 0x0 |
_RCON_BOR_POSITION | none | 0x0 |
_RCON_BOR_SIZE | none | 0x1 |
_RCON_BOR_LENGTH | none | 0x1 |
_RCON_BOR_MASK | none | 0x1 |
_RCON_POR_POSN | none | 0x1 |
_RCON_POR_POSITION | none | 0x1 |
_RCON_POR_SIZE | none | 0x1 |
_RCON_POR_LENGTH | none | 0x1 |
_RCON_POR_MASK | none | 0x2 |
_RCON_PD_POSN | none | 0x2 |
_RCON_PD_POSITION | none | 0x2 |
_RCON_PD_SIZE | none | 0x1 |
_RCON_PD_LENGTH | none | 0x1 |
_RCON_PD_MASK | none | 0x4 |
_RCON_TO_POSN | none | 0x3 |
_RCON_TO_POSITION | none | 0x3 |
_RCON_TO_SIZE | none | 0x1 |
_RCON_TO_LENGTH | none | 0x1 |
_RCON_TO_MASK | none | 0x8 |
_RCON_RI_POSN | none | 0x4 |
_RCON_RI_POSITION | none | 0x4 |
_RCON_RI_SIZE | none | 0x1 |
_RCON_RI_LENGTH | none | 0x1 |
_RCON_RI_MASK | none | 0x10 |
_RCON_nIPEN_POSN | none | 0x7 |
_RCON_nIPEN_POSITION | none | 0x7 |
_RCON_nIPEN_SIZE | none | 0x1 |
_RCON_nIPEN_LENGTH | none | 0x1 |
_RCON_nIPEN_MASK | none | 0x80 |
_WDTCON_SWDTEN_POSN | none | 0x0 |
_WDTCON_SWDTEN_POSITION | none | 0x0 |
_WDTCON_SWDTEN_SIZE | none | 0x1 |
_WDTCON_SWDTEN_LENGTH | none | 0x1 |
_WDTCON_SWDTEN_MASK | none | 0x1 |
_WDTCON_SWDTE_POSN | none | 0x0 |
_WDTCON_SWDTE_POSITION | none | 0x0 |
_WDTCON_SWDTE_SIZE | none | 0x1 |
_WDTCON_SWDTE_LENGTH | none | 0x1 |
_WDTCON_SWDTE_MASK | none | 0x1 |
_HLVDCON_HLVDL_POSN | none | 0x0 |
_HLVDCON_HLVDL_POSITION | none | 0x0 |
_HLVDCON_HLVDL_SIZE | none | 0x4 |
_HLVDCON_HLVDL_LENGTH | none | 0x4 |
_HLVDCON_HLVDL_MASK | none | 0xF |
_HLVDCON_HLVDEN_POSN | none | 0x4 |
_HLVDCON_HLVDEN_POSITION | none | 0x4 |
_HLVDCON_HLVDEN_SIZE | none | 0x1 |
_HLVDCON_HLVDEN_LENGTH | none | 0x1 |
_HLVDCON_HLVDEN_MASK | none | 0x10 |
_HLVDCON_IRVST_POSN | none | 0x5 |
_HLVDCON_IRVST_POSITION | none | 0x5 |
_HLVDCON_IRVST_SIZE | none | 0x1 |
_HLVDCON_IRVST_LENGTH | none | 0x1 |
_HLVDCON_IRVST_MASK | none | 0x20 |
_HLVDCON_VDIRMAG_POSN | none | 0x7 |
_HLVDCON_VDIRMAG_POSITION | none | 0x7 |
_HLVDCON_VDIRMAG_SIZE | none | 0x1 |
_HLVDCON_VDIRMAG_LENGTH | none | 0x1 |
_HLVDCON_VDIRMAG_MASK | none | 0x80 |
_HLVDCON_HLVDL0_POSN | none | 0x0 |
_HLVDCON_HLVDL0_POSITION | none | 0x0 |
_HLVDCON_HLVDL0_SIZE | none | 0x1 |
_HLVDCON_HLVDL0_LENGTH | none | 0x1 |
_HLVDCON_HLVDL0_MASK | none | 0x1 |
_HLVDCON_HLVDL1_POSN | none | 0x1 |
_HLVDCON_HLVDL1_POSITION | none | 0x1 |
_HLVDCON_HLVDL1_SIZE | none | 0x1 |
_HLVDCON_HLVDL1_LENGTH | none | 0x1 |
_HLVDCON_HLVDL1_MASK | none | 0x2 |
_HLVDCON_HLVDL2_POSN | none | 0x2 |
_HLVDCON_HLVDL2_POSITION | none | 0x2 |
_HLVDCON_HLVDL2_SIZE | none | 0x1 |
_HLVDCON_HLVDL2_LENGTH | none | 0x1 |
_HLVDCON_HLVDL2_MASK | none | 0x4 |
_HLVDCON_HLVDL3_POSN | none | 0x3 |
_HLVDCON_HLVDL3_POSITION | none | 0x3 |
_HLVDCON_HLVDL3_SIZE | none | 0x1 |
_HLVDCON_HLVDL3_LENGTH | none | 0x1 |
_HLVDCON_HLVDL3_MASK | none | 0x8 |
_HLVDCON_LVDL0_POSN | none | 0x0 |
_HLVDCON_LVDL0_POSITION | none | 0x0 |
_HLVDCON_LVDL0_SIZE | none | 0x1 |
_HLVDCON_LVDL0_LENGTH | none | 0x1 |
_HLVDCON_LVDL0_MASK | none | 0x1 |
_HLVDCON_LVDL1_POSN | none | 0x1 |
_HLVDCON_LVDL1_POSITION | none | 0x1 |
_HLVDCON_LVDL1_SIZE | none | 0x1 |
_HLVDCON_LVDL1_LENGTH | none | 0x1 |
_HLVDCON_LVDL1_MASK | none | 0x2 |
_HLVDCON_LVDL2_POSN | none | 0x2 |
_HLVDCON_LVDL2_POSITION | none | 0x2 |
_HLVDCON_LVDL2_SIZE | none | 0x1 |
_HLVDCON_LVDL2_LENGTH | none | 0x1 |
_HLVDCON_LVDL2_MASK | none | 0x4 |
_HLVDCON_LVDL3_POSN | none | 0x3 |
_HLVDCON_LVDL3_POSITION | none | 0x3 |
_HLVDCON_LVDL3_SIZE | none | 0x1 |
_HLVDCON_LVDL3_LENGTH | none | 0x1 |
_HLVDCON_LVDL3_MASK | none | 0x8 |
_HLVDCON_LVDEN_POSN | none | 0x4 |
_HLVDCON_LVDEN_POSITION | none | 0x4 |
_HLVDCON_LVDEN_SIZE | none | 0x1 |
_HLVDCON_LVDEN_LENGTH | none | 0x1 |
_HLVDCON_LVDEN_MASK | none | 0x10 |
_HLVDCON_IVRST_POSN | none | 0x5 |
_HLVDCON_IVRST_POSITION | none | 0x5 |
_HLVDCON_IVRST_SIZE | none | 0x1 |
_HLVDCON_IVRST_LENGTH | none | 0x1 |
_HLVDCON_IVRST_MASK | none | 0x20 |
_HLVDCON_LVV0_POSN | none | 0x0 |
_HLVDCON_LVV0_POSITION | none | 0x0 |
_HLVDCON_LVV0_SIZE | none | 0x1 |
_HLVDCON_LVV0_LENGTH | none | 0x1 |
_HLVDCON_LVV0_MASK | none | 0x1 |
_HLVDCON_LVV1_POSN | none | 0x1 |
_HLVDCON_LVV1_POSITION | none | 0x1 |
_HLVDCON_LVV1_SIZE | none | 0x1 |
_HLVDCON_LVV1_LENGTH | none | 0x1 |
_HLVDCON_LVV1_MASK | none | 0x2 |
_HLVDCON_LVV2_POSN | none | 0x2 |
_HLVDCON_LVV2_POSITION | none | 0x2 |
_HLVDCON_LVV2_SIZE | none | 0x1 |
_HLVDCON_LVV2_LENGTH | none | 0x1 |
_HLVDCON_LVV2_MASK | none | 0x4 |
_HLVDCON_LVV3_POSN | none | 0x3 |
_HLVDCON_LVV3_POSITION | none | 0x3 |
_HLVDCON_LVV3_SIZE | none | 0x1 |
_HLVDCON_LVV3_LENGTH | none | 0x1 |
_HLVDCON_LVV3_MASK | none | 0x8 |
_HLVDCON_BGST_POSN | none | 0x5 |
_HLVDCON_BGST_POSITION | none | 0x5 |
_HLVDCON_BGST_SIZE | none | 0x1 |
_HLVDCON_BGST_LENGTH | none | 0x1 |
_HLVDCON_BGST_MASK | none | 0x20 |
_LVDCON_HLVDL_POSN | none | 0x0 |
_LVDCON_HLVDL_POSITION | none | 0x0 |
_LVDCON_HLVDL_SIZE | none | 0x4 |
_LVDCON_HLVDL_LENGTH | none | 0x4 |
_LVDCON_HLVDL_MASK | none | 0xF |
_LVDCON_HLVDEN_POSN | none | 0x4 |
_LVDCON_HLVDEN_POSITION | none | 0x4 |
_LVDCON_HLVDEN_SIZE | none | 0x1 |
_LVDCON_HLVDEN_LENGTH | none | 0x1 |
_LVDCON_HLVDEN_MASK | none | 0x10 |
_LVDCON_IRVST_POSN | none | 0x5 |
_LVDCON_IRVST_POSITION | none | 0x5 |
_LVDCON_IRVST_SIZE | none | 0x1 |
_LVDCON_IRVST_LENGTH | none | 0x1 |
_LVDCON_IRVST_MASK | none | 0x20 |
_LVDCON_VDIRMAG_POSN | none | 0x7 |
_LVDCON_VDIRMAG_POSITION | none | 0x7 |
_LVDCON_VDIRMAG_SIZE | none | 0x1 |
_LVDCON_VDIRMAG_LENGTH | none | 0x1 |
_LVDCON_VDIRMAG_MASK | none | 0x80 |
_LVDCON_HLVDL0_POSN | none | 0x0 |
_LVDCON_HLVDL0_POSITION | none | 0x0 |
_LVDCON_HLVDL0_SIZE | none | 0x1 |
_LVDCON_HLVDL0_LENGTH | none | 0x1 |
_LVDCON_HLVDL0_MASK | none | 0x1 |
_LVDCON_HLVDL1_POSN | none | 0x1 |
_LVDCON_HLVDL1_POSITION | none | 0x1 |
_LVDCON_HLVDL1_SIZE | none | 0x1 |
_LVDCON_HLVDL1_LENGTH | none | 0x1 |
_LVDCON_HLVDL1_MASK | none | 0x2 |
_LVDCON_HLVDL2_POSN | none | 0x2 |
_LVDCON_HLVDL2_POSITION | none | 0x2 |
_LVDCON_HLVDL2_SIZE | none | 0x1 |
_LVDCON_HLVDL2_LENGTH | none | 0x1 |
_LVDCON_HLVDL2_MASK | none | 0x4 |
_LVDCON_HLVDL3_POSN | none | 0x3 |
_LVDCON_HLVDL3_POSITION | none | 0x3 |
_LVDCON_HLVDL3_SIZE | none | 0x1 |
_LVDCON_HLVDL3_LENGTH | none | 0x1 |
_LVDCON_HLVDL3_MASK | none | 0x8 |
_LVDCON_LVDL0_POSN | none | 0x0 |
_LVDCON_LVDL0_POSITION | none | 0x0 |
_LVDCON_LVDL0_SIZE | none | 0x1 |
_LVDCON_LVDL0_LENGTH | none | 0x1 |
_LVDCON_LVDL0_MASK | none | 0x1 |
_LVDCON_LVDL1_POSN | none | 0x1 |
_LVDCON_LVDL1_POSITION | none | 0x1 |
_LVDCON_LVDL1_SIZE | none | 0x1 |
_LVDCON_LVDL1_LENGTH | none | 0x1 |
_LVDCON_LVDL1_MASK | none | 0x2 |
_LVDCON_LVDL2_POSN | none | 0x2 |
_LVDCON_LVDL2_POSITION | none | 0x2 |
_LVDCON_LVDL2_SIZE | none | 0x1 |
_LVDCON_LVDL2_LENGTH | none | 0x1 |
_LVDCON_LVDL2_MASK | none | 0x4 |
_LVDCON_LVDL3_POSN | none | 0x3 |
_LVDCON_LVDL3_POSITION | none | 0x3 |
_LVDCON_LVDL3_SIZE | none | 0x1 |
_LVDCON_LVDL3_LENGTH | none | 0x1 |
_LVDCON_LVDL3_MASK | none | 0x8 |
_LVDCON_LVDEN_POSN | none | 0x4 |
_LVDCON_LVDEN_POSITION | none | 0x4 |
_LVDCON_LVDEN_SIZE | none | 0x1 |
_LVDCON_LVDEN_LENGTH | none | 0x1 |
_LVDCON_LVDEN_MASK | none | 0x10 |
_LVDCON_IVRST_POSN | none | 0x5 |
_LVDCON_IVRST_POSITION | none | 0x5 |
_LVDCON_IVRST_SIZE | none | 0x1 |
_LVDCON_IVRST_LENGTH | none | 0x1 |
_LVDCON_IVRST_MASK | none | 0x20 |
_LVDCON_LVV0_POSN | none | 0x0 |
_LVDCON_LVV0_POSITION | none | 0x0 |
_LVDCON_LVV0_SIZE | none | 0x1 |
_LVDCON_LVV0_LENGTH | none | 0x1 |
_LVDCON_LVV0_MASK | none | 0x1 |
_LVDCON_LVV1_POSN | none | 0x1 |
_LVDCON_LVV1_POSITION | none | 0x1 |
_LVDCON_LVV1_SIZE | none | 0x1 |
_LVDCON_LVV1_LENGTH | none | 0x1 |
_LVDCON_LVV1_MASK | none | 0x2 |
_LVDCON_LVV2_POSN | none | 0x2 |
_LVDCON_LVV2_POSITION | none | 0x2 |
_LVDCON_LVV2_SIZE | none | 0x1 |
_LVDCON_LVV2_LENGTH | none | 0x1 |
_LVDCON_LVV2_MASK | none | 0x4 |
_LVDCON_LVV3_POSN | none | 0x3 |
_LVDCON_LVV3_POSITION | none | 0x3 |
_LVDCON_LVV3_SIZE | none | 0x1 |
_LVDCON_LVV3_LENGTH | none | 0x1 |
_LVDCON_LVV3_MASK | none | 0x8 |
_LVDCON_BGST_POSN | none | 0x5 |
_LVDCON_BGST_POSITION | none | 0x5 |
_LVDCON_BGST_SIZE | none | 0x1 |
_LVDCON_BGST_LENGTH | none | 0x1 |
_LVDCON_BGST_MASK | none | 0x20 |
_OSCCON_SCS_POSN | none | 0x0 |
_OSCCON_SCS_POSITION | none | 0x0 |
_OSCCON_SCS_SIZE | none | 0x2 |
_OSCCON_SCS_LENGTH | none | 0x2 |
_OSCCON_SCS_MASK | none | 0x3 |
_OSCCON_IOFS_POSN | none | 0x2 |
_OSCCON_IOFS_POSITION | none | 0x2 |
_OSCCON_IOFS_SIZE | none | 0x1 |
_OSCCON_IOFS_LENGTH | none | 0x1 |
_OSCCON_IOFS_MASK | none | 0x4 |
_OSCCON_OSTS_POSN | none | 0x3 |
_OSCCON_OSTS_POSITION | none | 0x3 |
_OSCCON_OSTS_SIZE | none | 0x1 |
_OSCCON_OSTS_LENGTH | none | 0x1 |
_OSCCON_OSTS_MASK | none | 0x8 |
_OSCCON_IRCF_POSN | none | 0x4 |
_OSCCON_IRCF_POSITION | none | 0x4 |
_OSCCON_IRCF_SIZE | none | 0x3 |
_OSCCON_IRCF_LENGTH | none | 0x3 |
_OSCCON_IRCF_MASK | none | 0x70 |
_OSCCON_IDLEN_POSN | none | 0x7 |
_OSCCON_IDLEN_POSITION | none | 0x7 |
_OSCCON_IDLEN_SIZE | none | 0x1 |
_OSCCON_IDLEN_LENGTH | none | 0x1 |
_OSCCON_IDLEN_MASK | none | 0x80 |
_OSCCON_SCS0_POSN | none | 0x0 |
_OSCCON_SCS0_POSITION | none | 0x0 |
_OSCCON_SCS0_SIZE | none | 0x1 |
_OSCCON_SCS0_LENGTH | none | 0x1 |
_OSCCON_SCS0_MASK | none | 0x1 |
_OSCCON_SCS1_POSN | none | 0x1 |
_OSCCON_SCS1_POSITION | none | 0x1 |
_OSCCON_SCS1_SIZE | none | 0x1 |
_OSCCON_SCS1_LENGTH | none | 0x1 |
_OSCCON_SCS1_MASK | none | 0x2 |
_OSCCON_FLTS_POSN | none | 0x2 |
_OSCCON_FLTS_POSITION | none | 0x2 |
_OSCCON_FLTS_SIZE | none | 0x1 |
_OSCCON_FLTS_LENGTH | none | 0x1 |
_OSCCON_FLTS_MASK | none | 0x4 |
_OSCCON_IRCF0_POSN | none | 0x4 |
_OSCCON_IRCF0_POSITION | none | 0x4 |
_OSCCON_IRCF0_SIZE | none | 0x1 |
_OSCCON_IRCF0_LENGTH | none | 0x1 |
_OSCCON_IRCF0_MASK | none | 0x10 |
_OSCCON_IRCF1_POSN | none | 0x5 |
_OSCCON_IRCF1_POSITION | none | 0x5 |
_OSCCON_IRCF1_SIZE | none | 0x1 |
_OSCCON_IRCF1_LENGTH | none | 0x1 |
_OSCCON_IRCF1_MASK | none | 0x20 |
_OSCCON_IRCF2_POSN | none | 0x6 |
_OSCCON_IRCF2_POSITION | none | 0x6 |
_OSCCON_IRCF2_SIZE | none | 0x1 |
_OSCCON_IRCF2_LENGTH | none | 0x1 |
_OSCCON_IRCF2_MASK | none | 0x40 |
_T0CON_T0PS_POSN | none | 0x0 |
_T0CON_T0PS_POSITION | none | 0x0 |
_T0CON_T0PS_SIZE | none | 0x3 |
_T0CON_T0PS_LENGTH | none | 0x3 |
_T0CON_T0PS_MASK | none | 0x7 |
_T0CON_PSA_POSN | none | 0x3 |
_T0CON_PSA_POSITION | none | 0x3 |
_T0CON_PSA_SIZE | none | 0x1 |
_T0CON_PSA_LENGTH | none | 0x1 |
_T0CON_PSA_MASK | none | 0x8 |
_T0CON_T0SE_POSN | none | 0x4 |
_T0CON_T0SE_POSITION | none | 0x4 |
_T0CON_T0SE_SIZE | none | 0x1 |
_T0CON_T0SE_LENGTH | none | 0x1 |
_T0CON_T0SE_MASK | none | 0x10 |
_T0CON_T0CS_POSN | none | 0x5 |
_T0CON_T0CS_POSITION | none | 0x5 |
_T0CON_T0CS_SIZE | none | 0x1 |
_T0CON_T0CS_LENGTH | none | 0x1 |
_T0CON_T0CS_MASK | none | 0x20 |
_T0CON_T08BIT_POSN | none | 0x6 |
_T0CON_T08BIT_POSITION | none | 0x6 |
_T0CON_T08BIT_SIZE | none | 0x1 |
_T0CON_T08BIT_LENGTH | none | 0x1 |
_T0CON_T08BIT_MASK | none | 0x40 |
_T0CON_TMR0ON_POSN | none | 0x7 |
_T0CON_TMR0ON_POSITION | none | 0x7 |
_T0CON_TMR0ON_SIZE | none | 0x1 |
_T0CON_TMR0ON_LENGTH | none | 0x1 |
_T0CON_TMR0ON_MASK | none | 0x80 |
_T0CON_T0PS0_POSN | none | 0x0 |
_T0CON_T0PS0_POSITION | none | 0x0 |
_T0CON_T0PS0_SIZE | none | 0x1 |
_T0CON_T0PS0_LENGTH | none | 0x1 |
_T0CON_T0PS0_MASK | none | 0x1 |
_T0CON_T0PS1_POSN | none | 0x1 |
_T0CON_T0PS1_POSITION | none | 0x1 |
_T0CON_T0PS1_SIZE | none | 0x1 |
_T0CON_T0PS1_LENGTH | none | 0x1 |
_T0CON_T0PS1_MASK | none | 0x2 |
_T0CON_T0PS2_POSN | none | 0x2 |
_T0CON_T0PS2_POSITION | none | 0x2 |
_T0CON_T0PS2_SIZE | none | 0x1 |
_T0CON_T0PS2_LENGTH | none | 0x1 |
_T0CON_T0PS2_MASK | none | 0x4 |
_STATUS_C_POSN | none | 0x0 |
_STATUS_C_POSITION | none | 0x0 |
_STATUS_C_SIZE | none | 0x1 |
_STATUS_C_LENGTH | none | 0x1 |
_STATUS_C_MASK | none | 0x1 |
_STATUS_DC_POSN | none | 0x1 |
_STATUS_DC_POSITION | none | 0x1 |
_STATUS_DC_SIZE | none | 0x1 |
_STATUS_DC_LENGTH | none | 0x1 |
_STATUS_DC_MASK | none | 0x2 |
_STATUS_Z_POSN | none | 0x2 |
_STATUS_Z_POSITION | none | 0x2 |
_STATUS_Z_SIZE | none | 0x1 |
_STATUS_Z_LENGTH | none | 0x1 |
_STATUS_Z_MASK | none | 0x4 |
_STATUS_OV_POSN | none | 0x3 |
_STATUS_OV_POSITION | none | 0x3 |
_STATUS_OV_SIZE | none | 0x1 |
_STATUS_OV_LENGTH | none | 0x1 |
_STATUS_OV_MASK | none | 0x8 |
_STATUS_N_POSN | none | 0x4 |
_STATUS_N_POSITION | none | 0x4 |
_STATUS_N_SIZE | none | 0x1 |
_STATUS_N_LENGTH | none | 0x1 |
_STATUS_N_MASK | none | 0x10 |
_STATUS_CARRY_POSN | none | 0x0 |
_STATUS_CARRY_POSITION | none | 0x0 |
_STATUS_CARRY_SIZE | none | 0x1 |
_STATUS_CARRY_LENGTH | none | 0x1 |
_STATUS_CARRY_MASK | none | 0x1 |
_STATUS_NEGATIVE_POSN | none | 0x4 |
_STATUS_NEGATIVE_POSITION | none | 0x4 |
_STATUS_NEGATIVE_SIZE | none | 0x1 |
_STATUS_NEGATIVE_LENGTH | none | 0x1 |
_STATUS_NEGATIVE_MASK | none | 0x10 |
_STATUS_OVERFLOW_POSN | none | 0x3 |
_STATUS_OVERFLOW_POSITION | none | 0x3 |
_STATUS_OVERFLOW_SIZE | none | 0x1 |
_STATUS_OVERFLOW_LENGTH | none | 0x1 |
_STATUS_OVERFLOW_MASK | none | 0x8 |
_STATUS_ZERO_POSN | none | 0x2 |
_STATUS_ZERO_POSITION | none | 0x2 |
_STATUS_ZERO_SIZE | none | 0x1 |
_STATUS_ZERO_LENGTH | none | 0x1 |
_STATUS_ZERO_MASK | none | 0x4 |
_INTCON3_INT1IF_POSN | none | 0x0 |
_INTCON3_INT1IF_POSITION | none | 0x0 |
_INTCON3_INT1IF_SIZE | none | 0x1 |
_INTCON3_INT1IF_LENGTH | none | 0x1 |
_INTCON3_INT1IF_MASK | none | 0x1 |
_INTCON3_INT2IF_POSN | none | 0x1 |
_INTCON3_INT2IF_POSITION | none | 0x1 |
_INTCON3_INT2IF_SIZE | none | 0x1 |
_INTCON3_INT2IF_LENGTH | none | 0x1 |
_INTCON3_INT2IF_MASK | none | 0x2 |
_INTCON3_INT1IE_POSN | none | 0x3 |
_INTCON3_INT1IE_POSITION | none | 0x3 |
_INTCON3_INT1IE_SIZE | none | 0x1 |
_INTCON3_INT1IE_LENGTH | none | 0x1 |
_INTCON3_INT1IE_MASK | none | 0x8 |
_INTCON3_INT2IE_POSN | none | 0x4 |
_INTCON3_INT2IE_POSITION | none | 0x4 |
_INTCON3_INT2IE_SIZE | none | 0x1 |
_INTCON3_INT2IE_LENGTH | none | 0x1 |
_INTCON3_INT2IE_MASK | none | 0x10 |
_INTCON3_INT1IP_POSN | none | 0x6 |
_INTCON3_INT1IP_POSITION | none | 0x6 |
_INTCON3_INT1IP_SIZE | none | 0x1 |
_INTCON3_INT1IP_LENGTH | none | 0x1 |
_INTCON3_INT1IP_MASK | none | 0x40 |
_INTCON3_INT2IP_POSN | none | 0x7 |
_INTCON3_INT2IP_POSITION | none | 0x7 |
_INTCON3_INT2IP_SIZE | none | 0x1 |
_INTCON3_INT2IP_LENGTH | none | 0x1 |
_INTCON3_INT2IP_MASK | none | 0x80 |
_INTCON3_INT1F_POSN | none | 0x0 |
_INTCON3_INT1F_POSITION | none | 0x0 |
_INTCON3_INT1F_SIZE | none | 0x1 |
_INTCON3_INT1F_LENGTH | none | 0x1 |
_INTCON3_INT1F_MASK | none | 0x1 |
_INTCON3_INT2F_POSN | none | 0x1 |
_INTCON3_INT2F_POSITION | none | 0x1 |
_INTCON3_INT2F_SIZE | none | 0x1 |
_INTCON3_INT2F_LENGTH | none | 0x1 |
_INTCON3_INT2F_MASK | none | 0x2 |
_INTCON3_INT1E_POSN | none | 0x3 |
_INTCON3_INT1E_POSITION | none | 0x3 |
_INTCON3_INT1E_SIZE | none | 0x1 |
_INTCON3_INT1E_LENGTH | none | 0x1 |
_INTCON3_INT1E_MASK | none | 0x8 |
_INTCON3_INT2E_POSN | none | 0x4 |
_INTCON3_INT2E_POSITION | none | 0x4 |
_INTCON3_INT2E_SIZE | none | 0x1 |
_INTCON3_INT2E_LENGTH | none | 0x1 |
_INTCON3_INT2E_MASK | none | 0x10 |
_INTCON3_INT1P_POSN | none | 0x6 |
_INTCON3_INT1P_POSITION | none | 0x6 |
_INTCON3_INT1P_SIZE | none | 0x1 |
_INTCON3_INT1P_LENGTH | none | 0x1 |
_INTCON3_INT1P_MASK | none | 0x40 |
_INTCON3_INT2P_POSN | none | 0x7 |
_INTCON3_INT2P_POSITION | none | 0x7 |
_INTCON3_INT2P_SIZE | none | 0x1 |
_INTCON3_INT2P_LENGTH | none | 0x1 |
_INTCON3_INT2P_MASK | none | 0x80 |
_INTCON2_NOT_RBPU_POSN | none | 0x7 |
_INTCON2_NOT_RBPU_POSITION | none | 0x7 |
_INTCON2_NOT_RBPU_SIZE | none | 0x1 |
_INTCON2_NOT_RBPU_LENGTH | none | 0x1 |
_INTCON2_NOT_RBPU_MASK | none | 0x80 |
_INTCON2_RBIP_POSN | none | 0x0 |
_INTCON2_RBIP_POSITION | none | 0x0 |
_INTCON2_RBIP_SIZE | none | 0x1 |
_INTCON2_RBIP_LENGTH | none | 0x1 |
_INTCON2_RBIP_MASK | none | 0x1 |
_INTCON2_TMR0IP_POSN | none | 0x2 |
_INTCON2_TMR0IP_POSITION | none | 0x2 |
_INTCON2_TMR0IP_SIZE | none | 0x1 |
_INTCON2_TMR0IP_LENGTH | none | 0x1 |
_INTCON2_TMR0IP_MASK | none | 0x4 |
_INTCON2_INTEDG2_POSN | none | 0x4 |
_INTCON2_INTEDG2_POSITION | none | 0x4 |
_INTCON2_INTEDG2_SIZE | none | 0x1 |
_INTCON2_INTEDG2_LENGTH | none | 0x1 |
_INTCON2_INTEDG2_MASK | none | 0x10 |
_INTCON2_INTEDG1_POSN | none | 0x5 |
_INTCON2_INTEDG1_POSITION | none | 0x5 |
_INTCON2_INTEDG1_SIZE | none | 0x1 |
_INTCON2_INTEDG1_LENGTH | none | 0x1 |
_INTCON2_INTEDG1_MASK | none | 0x20 |
_INTCON2_INTEDG0_POSN | none | 0x6 |
_INTCON2_INTEDG0_POSITION | none | 0x6 |
_INTCON2_INTEDG0_SIZE | none | 0x1 |
_INTCON2_INTEDG0_LENGTH | none | 0x1 |
_INTCON2_INTEDG0_MASK | none | 0x40 |
_INTCON2_nRBPU_POSN | none | 0x7 |
_INTCON2_nRBPU_POSITION | none | 0x7 |
_INTCON2_nRBPU_SIZE | none | 0x1 |
_INTCON2_nRBPU_LENGTH | none | 0x1 |
_INTCON2_nRBPU_MASK | none | 0x80 |
_INTCON2_T0IP_POSN | none | 0x2 |
_INTCON2_T0IP_POSITION | none | 0x2 |
_INTCON2_T0IP_SIZE | none | 0x1 |
_INTCON2_T0IP_LENGTH | none | 0x1 |
_INTCON2_T0IP_MASK | none | 0x4 |
_INTCON2_RBPU_POSN | none | 0x7 |
_INTCON2_RBPU_POSITION | none | 0x7 |
_INTCON2_RBPU_SIZE | none | 0x1 |
_INTCON2_RBPU_LENGTH | none | 0x1 |
_INTCON2_RBPU_MASK | none | 0x80 |
_INTCON_RBIF_POSN | none | 0x0 |
_INTCON_RBIF_POSITION | none | 0x0 |
_INTCON_RBIF_SIZE | none | 0x1 |
_INTCON_RBIF_LENGTH | none | 0x1 |
_INTCON_RBIF_MASK | none | 0x1 |
_INTCON_INT0IF_POSN | none | 0x1 |
_INTCON_INT0IF_POSITION | none | 0x1 |
_INTCON_INT0IF_SIZE | none | 0x1 |
_INTCON_INT0IF_LENGTH | none | 0x1 |
_INTCON_INT0IF_MASK | none | 0x2 |
_INTCON_TMR0IF_POSN | none | 0x2 |
_INTCON_TMR0IF_POSITION | none | 0x2 |
_INTCON_TMR0IF_SIZE | none | 0x1 |
_INTCON_TMR0IF_LENGTH | none | 0x1 |
_INTCON_TMR0IF_MASK | none | 0x4 |
_INTCON_RBIE_POSN | none | 0x3 |
_INTCON_RBIE_POSITION | none | 0x3 |
_INTCON_RBIE_SIZE | none | 0x1 |
_INTCON_RBIE_LENGTH | none | 0x1 |
_INTCON_RBIE_MASK | none | 0x8 |
_INTCON_INT0IE_POSN | none | 0x4 |
_INTCON_INT0IE_POSITION | none | 0x4 |
_INTCON_INT0IE_SIZE | none | 0x1 |
_INTCON_INT0IE_LENGTH | none | 0x1 |
_INTCON_INT0IE_MASK | none | 0x10 |
_INTCON_TMR0IE_POSN | none | 0x5 |
_INTCON_TMR0IE_POSITION | none | 0x5 |
_INTCON_TMR0IE_SIZE | none | 0x1 |
_INTCON_TMR0IE_LENGTH | none | 0x1 |
_INTCON_TMR0IE_MASK | none | 0x20 |
_INTCON_PEIE_GIEL_POSN | none | 0x6 |
_INTCON_PEIE_GIEL_POSITION | none | 0x6 |
_INTCON_PEIE_GIEL_SIZE | none | 0x1 |
_INTCON_PEIE_GIEL_LENGTH | none | 0x1 |
_INTCON_PEIE_GIEL_MASK | none | 0x40 |
_INTCON_GIE_GIEH_POSN | none | 0x7 |
_INTCON_GIE_GIEH_POSITION | none | 0x7 |
_INTCON_GIE_GIEH_SIZE | none | 0x1 |
_INTCON_GIE_GIEH_LENGTH | none | 0x1 |
_INTCON_GIE_GIEH_MASK | none | 0x80 |
_INTCON_PEIE_POSN | none | 0x6 |
_INTCON_PEIE_POSITION | none | 0x6 |
_INTCON_PEIE_SIZE | none | 0x1 |
_INTCON_PEIE_LENGTH | none | 0x1 |
_INTCON_PEIE_MASK | none | 0x40 |
_INTCON_GIE_POSN | none | 0x7 |
_INTCON_GIE_POSITION | none | 0x7 |
_INTCON_GIE_SIZE | none | 0x1 |
_INTCON_GIE_LENGTH | none | 0x1 |
_INTCON_GIE_MASK | none | 0x80 |
_INTCON_GIEL_POSN | none | 0x6 |
_INTCON_GIEL_POSITION | none | 0x6 |
_INTCON_GIEL_SIZE | none | 0x1 |
_INTCON_GIEL_LENGTH | none | 0x1 |
_INTCON_GIEL_MASK | none | 0x40 |
_INTCON_GIEH_POSN | none | 0x7 |
_INTCON_GIEH_POSITION | none | 0x7 |
_INTCON_GIEH_SIZE | none | 0x1 |
_INTCON_GIEH_LENGTH | none | 0x1 |
_INTCON_GIEH_MASK | none | 0x80 |
_INTCON_INT0F_POSN | none | 0x1 |
_INTCON_INT0F_POSITION | none | 0x1 |
_INTCON_INT0F_SIZE | none | 0x1 |
_INTCON_INT0F_LENGTH | none | 0x1 |
_INTCON_INT0F_MASK | none | 0x2 |
_INTCON_T0IF_POSN | none | 0x2 |
_INTCON_T0IF_POSITION | none | 0x2 |
_INTCON_T0IF_SIZE | none | 0x1 |
_INTCON_T0IF_LENGTH | none | 0x1 |
_INTCON_T0IF_MASK | none | 0x4 |
_INTCON_INT0E_POSN | none | 0x4 |
_INTCON_INT0E_POSITION | none | 0x4 |
_INTCON_INT0E_SIZE | none | 0x1 |
_INTCON_INT0E_LENGTH | none | 0x1 |
_INTCON_INT0E_MASK | none | 0x10 |
_INTCON_T0IE_POSN | none | 0x5 |
_INTCON_T0IE_POSITION | none | 0x5 |
_INTCON_T0IE_SIZE | none | 0x1 |
_INTCON_T0IE_LENGTH | none | 0x1 |
_INTCON_T0IE_MASK | none | 0x20 |
_STKPTR_STKPTR_POSN | none | 0x0 |
_STKPTR_STKPTR_POSITION | none | 0x0 |
_STKPTR_STKPTR_SIZE | none | 0x5 |
_STKPTR_STKPTR_LENGTH | none | 0x5 |
_STKPTR_STKPTR_MASK | none | 0x1F |
_STKPTR_STKUNF_POSN | none | 0x6 |
_STKPTR_STKUNF_POSITION | none | 0x6 |
_STKPTR_STKUNF_SIZE | none | 0x1 |
_STKPTR_STKUNF_LENGTH | none | 0x1 |
_STKPTR_STKUNF_MASK | none | 0x40 |
_STKPTR_STKFUL_POSN | none | 0x7 |
_STKPTR_STKFUL_POSITION | none | 0x7 |
_STKPTR_STKFUL_SIZE | none | 0x1 |
_STKPTR_STKFUL_LENGTH | none | 0x1 |
_STKPTR_STKFUL_MASK | none | 0x80 |
_STKPTR_STKPTR0_POSN | none | 0x0 |
_STKPTR_STKPTR0_POSITION | none | 0x0 |
_STKPTR_STKPTR0_SIZE | none | 0x1 |
_STKPTR_STKPTR0_LENGTH | none | 0x1 |
_STKPTR_STKPTR0_MASK | none | 0x1 |
_STKPTR_STKPTR1_POSN | none | 0x1 |
_STKPTR_STKPTR1_POSITION | none | 0x1 |
_STKPTR_STKPTR1_SIZE | none | 0x1 |
_STKPTR_STKPTR1_LENGTH | none | 0x1 |
_STKPTR_STKPTR1_MASK | none | 0x2 |
_STKPTR_STKPTR2_POSN | none | 0x2 |
_STKPTR_STKPTR2_POSITION | none | 0x2 |
_STKPTR_STKPTR2_SIZE | none | 0x1 |
_STKPTR_STKPTR2_LENGTH | none | 0x1 |
_STKPTR_STKPTR2_MASK | none | 0x4 |
_STKPTR_STKPTR3_POSN | none | 0x3 |
_STKPTR_STKPTR3_POSITION | none | 0x3 |
_STKPTR_STKPTR3_SIZE | none | 0x1 |
_STKPTR_STKPTR3_LENGTH | none | 0x1 |
_STKPTR_STKPTR3_MASK | none | 0x8 |
_STKPTR_STKPTR4_POSN | none | 0x4 |
_STKPTR_STKPTR4_POSITION | none | 0x4 |
_STKPTR_STKPTR4_SIZE | none | 0x1 |
_STKPTR_STKPTR4_LENGTH | none | 0x1 |
_STKPTR_STKPTR4_MASK | none | 0x10 |
_STKPTR_STKOVF_POSN | none | 0x7 |
_STKPTR_STKOVF_POSITION | none | 0x7 |
_STKPTR_STKOVF_SIZE | none | 0x1 |
_STKPTR_STKOVF_LENGTH | none | 0x1 |
_STKPTR_STKOVF_MASK | none | 0x80 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
BANKMASK | 1 | ((<0>)&0FFh) |
ABDEN_bit | none | BANKMASK(BAUDCON), 0 |
ABDOVF_bit | none | BANKMASK(BAUDCON), 7 |
ACKDT_bit | none | BANKMASK(SSPCON2), 5 |
ACKEN_bit | none | BANKMASK(SSPCON2), 4 |
ACKSTAT_bit | none | BANKMASK(SSPCON2), 6 |
ACQT0_bit | none | BANKMASK(ADCON2), 3 |
ACQT1_bit | none | BANKMASK(ADCON2), 4 |
ACQT2_bit | none | BANKMASK(ADCON2), 5 |
ACTVIE_bit | none | BANKMASK(UIE), 2 |
ACTVIF_bit | none | BANKMASK(UIR), 2 |
ADCS0_bit | none | BANKMASK(ADCON2), 0 |
ADCS1_bit | none | BANKMASK(ADCON2), 1 |
ADCS2_bit | none | BANKMASK(ADCON2), 2 |
ADDEN_bit | none | BANKMASK(RCSTA), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
ADDR0_bit | none | BANKMASK(SPPEPS), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
ADDR1_bit | none | BANKMASK(SPPEPS), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
ADDR2_bit | none | BANKMASK(SPPEPS), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
ADDR3_bit | none | BANKMASK(SPPEPS), 3 |
ADDR4_bit | none | BANKMASK(UADDR), 4 |
ADDR5_bit | none | BANKMASK(UADDR), 5 |
ADDR6_bit | none | BANKMASK(UADDR), 6 |
ADEN_bit | none | BANKMASK(RCSTA), 3 |
ADFM_bit | none | BANKMASK(ADCON2), 7 |
ADIE_bit | none | BANKMASK(PIE1), 6 |
ADIF_bit | none | BANKMASK(PIR1), 6 |
ADIP_bit | none | BANKMASK(IPR1), 6 |
ADON_bit | none | BANKMASK(ADCON0), 0 |
AN0_bit | none | BANKMASK(PORTA), 0 |
AN1_bit | none | BANKMASK(PORTA), 1 |
AN2_bit | none | BANKMASK(PORTA), 2 |
AN3_bit | none | BANKMASK(PORTA), 3 |
AN4_bit | none | BANKMASK(PORTA), 5 |
BCLIE_bit | none | BANKMASK(PIE2), 3 |
BCLIF_bit | none | BANKMASK(PIR2), 3 |
BCLIP_bit | none | BANKMASK(IPR2), 3 |
BF_bit | none | BANKMASK(SSPSTAT), 0 |
BGST_bit | none | BANKMASK(HLVDCON), 5 |
BOR_bit | none | BANKMASK(RCON), 0 |
BRG16_bit | none | BANKMASK(BAUDCON), 3 |
BRGH_bit | none | BANKMASK(TXSTA), 2 |
BRGH1_bit | none | BANKMASK(TXSTA), 2 |
BTOEE_bit | none | BANKMASK(UEIE), 4 |
BTOEF_bit | none | BANKMASK(UEIR), 4 |
BTSEE_bit | none | BANKMASK(UEIE), 7 |
BTSEF_bit | none | BANKMASK(UEIR), 7 |
BUSY_bit | none | BANKMASK(SPPEPS), 4 |
C1INV_bit | none | BANKMASK(CMCON), 4 |
C1OUT_bit | none | BANKMASK(CMCON), 6 |
C2INV_bit | none | BANKMASK(CMCON), 5 |
C2OUT_bit | none | BANKMASK(CMCON), 7 |
CARRY_bit | none | BANKMASK(STATUS), 0 |
CCP1_bit | none | BANKMASK(PORTC), 2 |
CCP10_bit | none | BANKMASK(PORTE), 2 |
CCP1IE_bit | none | BANKMASK(PIE1), 2 |
CCP1IF_bit | none | BANKMASK(PIR1), 2 |
CCP1IP_bit | none | BANKMASK(IPR1), 2 |
CCP1M0_bit | none | BANKMASK(CCP1CON), 0 |
CCP1M1_bit | none | BANKMASK(CCP1CON), 1 |
CCP1M2_bit | none | BANKMASK(CCP1CON), 2 |
CCP1M3_bit | none | BANKMASK(CCP1CON), 3 |
CCP2_bit | none | BANKMASK(PORTC), 1 |
CCP2E_bit | none | BANKMASK(PORTE), 7 |
CCP2IE_bit | none | BANKMASK(PIE2), 0 |
CCP2IF_bit | none | BANKMASK(PIR2), 0 |
CCP2IP_bit | none | BANKMASK(IPR2), 0 |
CCP2M0_bit | none | BANKMASK(CCP2CON), 0 |
CCP2M1_bit | none | BANKMASK(CCP2CON), 1 |
CCP2M2_bit | none | BANKMASK(CCP2CON), 2 |
CCP2M3_bit | none | BANKMASK(CCP2CON), 3 |
CCP2_PA2_bit | none | BANKMASK(PORTB), 3 |
CCP6E_bit | none | BANKMASK(PORTE), 6 |
CCP7E_bit | none | BANKMASK(PORTE), 5 |
CCP8E_bit | none | BANKMASK(PORTE), 4 |
CCP9E_bit | none | BANKMASK(PORTE), 3 |
CFGS_bit | none | BANKMASK(EECON1), 6 |
CHS0_bit | none | BANKMASK(ADCON0), 2 |
CHS1_bit | none | BANKMASK(ADCON0), 3 |
CHS2_bit | none | BANKMASK(ADCON0), 4 |
CHS3_bit | none | BANKMASK(ADCON0), 5 |
CHSN3_bit | none | BANKMASK(ADCON1), 3 |
CIS_bit | none | BANKMASK(CMCON), 3 |
CK_bit | none | BANKMASK(PORTC), 6 |
CK1SPP_bit | none | BANKMASK(PORTE), 0 |
CK2SPP_bit | none | BANKMASK(PORTE), 1 |
CKE_bit | none | BANKMASK(SSPSTAT), 6 |
CKP_bit | none | BANKMASK(SSPCON1), 4 |
CLK1EN_bit | none | BANKMASK(SPPCFG), 4 |
CLKCFG0_bit | none | BANKMASK(SPPCFG), 6 |
CLKCFG1_bit | none | BANKMASK(SPPCFG), 7 |
CM0_bit | none | BANKMASK(CMCON), 0 |
CM1_bit | none | BANKMASK(CMCON), 1 |
CM2_bit | none | BANKMASK(CMCON), 2 |
CMEN0_bit | none | BANKMASK(CMCON), 0 |
CMEN1_bit | none | BANKMASK(CMCON), 1 |
CMEN2_bit | none | BANKMASK(CMCON), 2 |
CMIE_bit | none | BANKMASK(PIE2), 6 |
CMIF_bit | none | BANKMASK(PIR2), 6 |
CMIP_bit | none | BANKMASK(IPR2), 6 |
CRC16EE_bit | none | BANKMASK(UEIE), 2 |
CRC16EF_bit | none | BANKMASK(UEIR), 2 |
CRC5EE_bit | none | BANKMASK(UEIE), 1 |
CRC5EF_bit | none | BANKMASK(UEIR), 1 |
CREN_bit | none | BANKMASK(RCSTA), 4 |
CS_bit | none | BANKMASK(PORTE), 2 |
CSEN_bit | none | BANKMASK(SPPCFG), 5 |
CSRC_bit | none | BANKMASK(TXSTA), 7 |
CSRC1_bit | none | BANKMASK(TXSTA), 7 |
CVR0_bit | none | BANKMASK(CVRCON), 0 |
CVR1_bit | none | BANKMASK(CVRCON), 1 |
CVR2_bit | none | BANKMASK(CVRCON), 2 |
CVR3_bit | none | BANKMASK(CVRCON), 3 |
CVREF_bit | none | BANKMASK(CVRCON), 4 |
CVREN_bit | none | BANKMASK(CVRCON), 7 |
CVROE_bit | none | BANKMASK(CVRCON), 6 |
CVROEN_bit | none | BANKMASK(CVRCON), 6 |
CVRR_bit | none | BANKMASK(CVRCON), 5 |
CVRSS_bit | none | BANKMASK(CVRCON), 4 |
DA_bit | none | BANKMASK(SSPSTAT), 5 |
DATA_ADDRESS_bit | none | BANKMASK(SSPSTAT), 5 |
DC_bit | none | BANKMASK(STATUS), 1 |
DC1B0_bit | none | BANKMASK(CCP1CON), 4 |
DC1B1_bit | none | BANKMASK(CCP1CON), 5 |
DC2B0_bit | none | BANKMASK(CCP2CON), 4 |
DC2B1_bit | none | BANKMASK(CCP2CON), 5 |
DFN8EE_bit | none | BANKMASK(UEIE), 3 |
DFN8EF_bit | none | BANKMASK(UEIR), 3 |
DIR_bit | none | BANKMASK(USTAT), 2 |
DONE_bit | none | BANKMASK(ADCON0), 1 |
DT_bit | none | BANKMASK(PORTC), 7 |
D_A_bit | none | BANKMASK(SSPSTAT), 5 |
D_NOT_A_bit | none | BANKMASK(SSPSTAT), 5 |
D_nA_bit | none | BANKMASK(SSPSTAT), 5 |
EBDIS_bit | none | BANKMASK(PR2), 7 |
ECCPAS0_bit | none | BANKMASK(ECCP1AS), 4 |
ECCPAS1_bit | none | BANKMASK(ECCP1AS), 5 |
ECCPAS2_bit | none | BANKMASK(ECCP1AS), 6 |
ECCPASE_bit | none | BANKMASK(ECCP1AS), 7 |
EEFS_bit | none | BANKMASK(EECON1), 6 |
EEIE_bit | none | BANKMASK(PIE2), 4 |
EEIF_bit | none | BANKMASK(PIR2), 4 |
EEIP_bit | none | BANKMASK(IPR2), 4 |
EEPGD_bit | none | BANKMASK(EECON1), 7 |
ENDP0_bit | none | BANKMASK(USTAT), 3 |
ENDP1_bit | none | BANKMASK(USTAT), 4 |
ENDP2_bit | none | BANKMASK(USTAT), 5 |
ENDP3_bit | none | BANKMASK(USTAT), 6 |
EP0CONDIS_bit | none | BANKMASK(UEP0), 3 |
EP0HSHK_bit | none | BANKMASK(UEP0), 4 |
EP0INEN_bit | none | BANKMASK(UEP0), 1 |
EP0OUTEN_bit | none | BANKMASK(UEP0), 2 |
EP0STALL_bit | none | BANKMASK(UEP0), 0 |
EP1CONDIS_bit | none | BANKMASK(UEP1), 3 |
EP1HSHK_bit | none | BANKMASK(UEP1), 4 |
EP1INEN_bit | none | BANKMASK(UEP1), 1 |
EP1OUTEN_bit | none | BANKMASK(UEP1), 2 |
EP1STALL_bit | none | BANKMASK(UEP1), 0 |
EP2CONDIS_bit | none | BANKMASK(UEP2), 3 |
EP2HSHK_bit | none | BANKMASK(UEP2), 4 |
EP2INEN_bit | none | BANKMASK(UEP2), 1 |
EP2OUTEN_bit | none | BANKMASK(UEP2), 2 |
EP2STALL_bit | none | BANKMASK(UEP2), 0 |
EP3CONDIS_bit | none | BANKMASK(UEP3), 3 |
EP3HSHK_bit | none | BANKMASK(UEP3), 4 |
EP3INEN_bit | none | BANKMASK(UEP3), 1 |
EP3OUTEN_bit | none | BANKMASK(UEP3), 2 |
EP3STALL_bit | none | BANKMASK(UEP3), 0 |
EP4CONDIS_bit | none | BANKMASK(UEP4), 3 |
EP4HSHK_bit | none | BANKMASK(UEP4), 4 |
EP4INEN_bit | none | BANKMASK(UEP4), 1 |
EP4OUTEN_bit | none | BANKMASK(UEP4), 2 |
EP4STALL_bit | none | BANKMASK(UEP4), 0 |
EP5CONDIS_bit | none | BANKMASK(UEP5), 3 |
EP5HSHK_bit | none | BANKMASK(UEP5), 4 |
EP5INEN_bit | none | BANKMASK(UEP5), 1 |
EP5OUTEN_bit | none | BANKMASK(UEP5), 2 |
EP5STALL_bit | none | BANKMASK(UEP5), 0 |
EP6CONDIS_bit | none | BANKMASK(UEP6), 3 |
EP6HSHK_bit | none | BANKMASK(UEP6), 4 |
EP6INEN_bit | none | BANKMASK(UEP6), 1 |
EP6OUTEN_bit | none | BANKMASK(UEP6), 2 |
EP6STALL_bit | none | BANKMASK(UEP6), 0 |
EP7CONDIS_bit | none | BANKMASK(UEP7), 3 |
EP7HSHK_bit | none | BANKMASK(UEP7), 4 |
EP7INEN_bit | none | BANKMASK(UEP7), 1 |
EP7OUTEN_bit | none | BANKMASK(UEP7), 2 |
EP7STALL_bit | none | BANKMASK(UEP7), 0 |
EPCONDIS0_bit | none | BANKMASK(UEP0), 3 |
EPCONDIS1_bit | none | BANKMASK(UEP1), 3 |
EPCONDIS10_bit | none | BANKMASK(UEP10), 3 |
EPCONDIS11_bit | none | BANKMASK(UEP11), 3 |
EPCONDIS12_bit | none | BANKMASK(UEP12), 3 |
EPCONDIS13_bit | none | BANKMASK(UEP13), 3 |
EPCONDIS14_bit | none | BANKMASK(UEP14), 3 |
EPCONDIS15_bit | none | BANKMASK(UEP15), 3 |
EPCONDIS2_bit | none | BANKMASK(UEP2), 3 |
EPCONDIS3_bit | none | BANKMASK(UEP3), 3 |
EPCONDIS4_bit | none | BANKMASK(UEP4), 3 |
EPCONDIS5_bit | none | BANKMASK(UEP5), 3 |
EPCONDIS6_bit | none | BANKMASK(UEP6), 3 |
EPCONDIS7_bit | none | BANKMASK(UEP7), 3 |
EPCONDIS8_bit | none | BANKMASK(UEP8), 3 |
EPCONDIS9_bit | none | BANKMASK(UEP9), 3 |
EPHSHK0_bit | none | BANKMASK(UEP0), 4 |
EPHSHK1_bit | none | BANKMASK(UEP1), 4 |
EPHSHK10_bit | none | BANKMASK(UEP10), 4 |
EPHSHK11_bit | none | BANKMASK(UEP11), 4 |
EPHSHK12_bit | none | BANKMASK(UEP12), 4 |
EPHSHK13_bit | none | BANKMASK(UEP13), 4 |
EPHSHK14_bit | none | BANKMASK(UEP14), 4 |
EPHSHK15_bit | none | BANKMASK(UEP15), 4 |
EPHSHK2_bit | none | BANKMASK(UEP2), 4 |
EPHSHK3_bit | none | BANKMASK(UEP3), 4 |
EPHSHK4_bit | none | BANKMASK(UEP4), 4 |
EPHSHK5_bit | none | BANKMASK(UEP5), 4 |
EPHSHK6_bit | none | BANKMASK(UEP6), 4 |
EPHSHK7_bit | none | BANKMASK(UEP7), 4 |
EPHSHK8_bit | none | BANKMASK(UEP8), 4 |
EPHSHK9_bit | none | BANKMASK(UEP9), 4 |
EPINEN0_bit | none | BANKMASK(UEP0), 1 |
EPINEN1_bit | none | BANKMASK(UEP1), 1 |
EPINEN10_bit | none | BANKMASK(UEP10), 1 |
EPINEN11_bit | none | BANKMASK(UEP11), 1 |
EPINEN12_bit | none | BANKMASK(UEP12), 1 |
EPINEN13_bit | none | BANKMASK(UEP13), 1 |
EPINEN14_bit | none | BANKMASK(UEP14), 1 |
EPINEN15_bit | none | BANKMASK(UEP15), 1 |
EPINEN2_bit | none | BANKMASK(UEP2), 1 |
EPINEN3_bit | none | BANKMASK(UEP3), 1 |
EPINEN4_bit | none | BANKMASK(UEP4), 1 |
EPINEN5_bit | none | BANKMASK(UEP5), 1 |
EPINEN6_bit | none | BANKMASK(UEP6), 1 |
EPINEN7_bit | none | BANKMASK(UEP7), 1 |
EPINEN8_bit | none | BANKMASK(UEP8), 1 |
EPINEN9_bit | none | BANKMASK(UEP9), 1 |
EPOUTEN0_bit | none | BANKMASK(UEP0), 2 |
EPOUTEN1_bit | none | BANKMASK(UEP1), 2 |
EPOUTEN10_bit | none | BANKMASK(UEP10), 2 |
EPOUTEN11_bit | none | BANKMASK(UEP11), 2 |
EPOUTEN12_bit | none | BANKMASK(UEP12), 2 |
EPOUTEN13_bit | none | BANKMASK(UEP13), 2 |
EPOUTEN14_bit | none | BANKMASK(UEP14), 2 |
EPOUTEN15_bit | none | BANKMASK(UEP15), 2 |
EPOUTEN2_bit | none | BANKMASK(UEP2), 2 |
EPOUTEN3_bit | none | BANKMASK(UEP3), 2 |
EPOUTEN4_bit | none | BANKMASK(UEP4), 2 |
EPOUTEN5_bit | none | BANKMASK(UEP5), 2 |
EPOUTEN6_bit | none | BANKMASK(UEP6), 2 |
EPOUTEN7_bit | none | BANKMASK(UEP7), 2 |
EPOUTEN8_bit | none | BANKMASK(UEP8), 2 |
EPOUTEN9_bit | none | BANKMASK(UEP9), 2 |
EPSTALL0_bit | none | BANKMASK(UEP0), 0 |
EPSTALL1_bit | none | BANKMASK(UEP1), 0 |
EPSTALL10_bit | none | BANKMASK(UEP10), 0 |
EPSTALL11_bit | none | BANKMASK(UEP11), 0 |
EPSTALL12_bit | none | BANKMASK(UEP12), 0 |
EPSTALL13_bit | none | BANKMASK(UEP13), 0 |
EPSTALL14_bit | none | BANKMASK(UEP14), 0 |
EPSTALL15_bit | none | BANKMASK(UEP15), 0 |
EPSTALL2_bit | none | BANKMASK(UEP2), 0 |
EPSTALL3_bit | none | BANKMASK(UEP3), 0 |
EPSTALL4_bit | none | BANKMASK(UEP4), 0 |
EPSTALL5_bit | none | BANKMASK(UEP5), 0 |
EPSTALL6_bit | none | BANKMASK(UEP6), 0 |
EPSTALL7_bit | none | BANKMASK(UEP7), 0 |
EPSTALL8_bit | none | BANKMASK(UEP8), 0 |
EPSTALL9_bit | none | BANKMASK(UEP9), 0 |
FERR_bit | none | BANKMASK(RCSTA), 2 |
FLTS_bit | none | BANKMASK(OSCCON), 2 |
FREE_bit | none | BANKMASK(EECON1), 4 |
FRM0_bit | none | BANKMASK(UFRML), 0 |
FRM1_bit | none | BANKMASK(UFRML), 1 |
FRM10_bit | none | BANKMASK(UFRMH), 2 |
FRM2_bit | none | BANKMASK(UFRML), 2 |
FRM3_bit | none | BANKMASK(UFRML), 3 |
FRM4_bit | none | BANKMASK(UFRML), 4 |
FRM5_bit | none | BANKMASK(UFRML), 5 |
FRM6_bit | none | BANKMASK(UFRML), 6 |
FRM7_bit | none | BANKMASK(UFRML), 7 |
FRM8_bit | none | BANKMASK(UFRMH), 0 |
FRM9_bit | none | BANKMASK(UFRMH), 1 |
FSEN_bit | none | BANKMASK(UCFG), 2 |
GCEN_bit | none | BANKMASK(SSPCON2), 7 |
GIE_bit | none | BANKMASK(INTCON), 7 |
GIEH_bit | none | BANKMASK(INTCON), 7 |
GIEL_bit | none | BANKMASK(INTCON), 6 |
GIE_GIEH_bit | none | BANKMASK(INTCON), 7 |
GO_bit | none | BANKMASK(ADCON0), 1 |
GODONE_bit | none | BANKMASK(ADCON0), 1 |
GO_DONE_bit | none | BANKMASK(ADCON0), 1 |
GO_NOT_DONE_bit | none | BANKMASK(ADCON0), 1 |
GO_nDONE_bit | none | BANKMASK(ADCON0), 1 |
HLVDEN_bit | none | BANKMASK(HLVDCON), 4 |
HLVDIE_bit | none | BANKMASK(PIE2), 2 |
HLVDIF_bit | none | BANKMASK(PIR2), 2 |
HLVDIN_bit | none | BANKMASK(PORTA), 5 |
HLVDIP_bit | none | BANKMASK(IPR2), 2 |
HLVDL0_bit | none | BANKMASK(HLVDCON), 0 |
HLVDL1_bit | none | BANKMASK(HLVDCON), 1 |
HLVDL2_bit | none | BANKMASK(HLVDCON), 2 |
HLVDL3_bit | none | BANKMASK(HLVDCON), 3 |
I2C_DAT_bit | none | BANKMASK(SSPSTAT), 5 |
I2C_READ_bit | none | BANKMASK(SSPSTAT), 2 |
I2C_START_bit | none | BANKMASK(SSPSTAT), 3 |
I2C_STOP_bit | none | BANKMASK(SSPSTAT), 4 |
IDLEIE_bit | none | BANKMASK(UIE), 4 |
IDLEIF_bit | none | BANKMASK(UIR), 4 |
IDLEN_bit | none | BANKMASK(OSCCON), 7 |
INT0_bit | none | BANKMASK(PORTB), 0 |
INT0E_bit | none | BANKMASK(INTCON), 4 |
INT0F_bit | none | BANKMASK(INTCON), 1 |
INT0IE_bit | none | BANKMASK(INTCON), 4 |
INT0IF_bit | none | BANKMASK(INTCON), 1 |
INT1_bit | none | BANKMASK(PORTB), 1 |
INT1E_bit | none | BANKMASK(INTCON3), 3 |
INT1F_bit | none | BANKMASK(INTCON3), 0 |
INT1IE_bit | none | BANKMASK(INTCON3), 3 |
INT1IF_bit | none | BANKMASK(INTCON3), 0 |
INT1IP_bit | none | BANKMASK(INTCON3), 6 |
INT1P_bit | none | BANKMASK(INTCON3), 6 |
INT2_bit | none | BANKMASK(PORTB), 2 |
INT2E_bit | none | BANKMASK(INTCON3), 4 |
INT2F_bit | none | BANKMASK(INTCON3), 1 |
INT2IE_bit | none | BANKMASK(INTCON3), 4 |
INT2IF_bit | none | BANKMASK(INTCON3), 1 |
INT2IP_bit | none | BANKMASK(INTCON3), 7 |
INT2P_bit | none | BANKMASK(INTCON3), 7 |
INTEDG0_bit | none | BANKMASK(INTCON2), 6 |
INTEDG1_bit | none | BANKMASK(INTCON2), 5 |
INTEDG2_bit | none | BANKMASK(INTCON2), 4 |
INTSRC_bit | none | BANKMASK(OSCTUNE), 7 |
IOFS_bit | none | BANKMASK(OSCCON), 2 |
IPEN_bit | none | BANKMASK(RCON), 7 |
IRCF0_bit | none | BANKMASK(OSCCON), 4 |
IRCF1_bit | none | BANKMASK(OSCCON), 5 |
IRCF2_bit | none | BANKMASK(OSCCON), 6 |
IRVST_bit | none | BANKMASK(HLVDCON), 5 |
IVRST_bit | none | BANKMASK(HLVDCON), 5 |
LA0_bit | none | BANKMASK(LATA), 0 |
LA1_bit | none | BANKMASK(LATA), 1 |
LA2_bit | none | BANKMASK(LATA), 2 |
LA3_bit | none | BANKMASK(LATA), 3 |
LA4_bit | none | BANKMASK(LATA), 4 |
LA5_bit | none | BANKMASK(LATA), 5 |
LA6_bit | none | BANKMASK(LATA), 6 |
LA7_bit | none | BANKMASK(LATA), 7 |
LATA0_bit | none | BANKMASK(LATA), 0 |
LATA1_bit | none | BANKMASK(LATA), 1 |
LATA2_bit | none | BANKMASK(LATA), 2 |
LATA3_bit | none | BANKMASK(LATA), 3 |
LATA4_bit | none | BANKMASK(LATA), 4 |
LATA5_bit | none | BANKMASK(LATA), 5 |
LATA6_bit | none | BANKMASK(LATA), 6 |
LATA7_bit | none | BANKMASK(LATA), 7 |
LATB0_bit | none | BANKMASK(LATB), 0 |
LATB1_bit | none | BANKMASK(LATB), 1 |
LATB2_bit | none | BANKMASK(LATB), 2 |
LATB3_bit | none | BANKMASK(LATB), 3 |
LATB4_bit | none | BANKMASK(LATB), 4 |
LATB5_bit | none | BANKMASK(LATB), 5 |
LATB6_bit | none | BANKMASK(LATB), 6 |
LATB7_bit | none | BANKMASK(LATB), 7 |
LATC0_bit | none | BANKMASK(LATC), 0 |
LATC1_bit | none | BANKMASK(LATC), 1 |
LATC2_bit | none | BANKMASK(LATC), 2 |
LATC6_bit | none | BANKMASK(LATC), 6 |
LATC7_bit | none | BANKMASK(LATC), 7 |
LATD0_bit | none | BANKMASK(LATD), 0 |
LATD1_bit | none | BANKMASK(LATD), 1 |
LATD2_bit | none | BANKMASK(LATD), 2 |
LATD3_bit | none | BANKMASK(LATD), 3 |
LATD4_bit | none | BANKMASK(LATD), 4 |
LATD5_bit | none | BANKMASK(LATD), 5 |
LATD6_bit | none | BANKMASK(LATD), 6 |
LATD7_bit | none | BANKMASK(LATD), 7 |
LATE0_bit | none | BANKMASK(LATE), 0 |
LATE1_bit | none | BANKMASK(LATE), 1 |
LATE2_bit | none | BANKMASK(LATE), 2 |
LB0_bit | none | BANKMASK(LATB), 0 |
LB1_bit | none | BANKMASK(LATB), 1 |
LB2_bit | none | BANKMASK(LATB), 2 |
LB3_bit | none | BANKMASK(LATB), 3 |
LB4_bit | none | BANKMASK(LATB), 4 |
LB5_bit | none | BANKMASK(LATB), 5 |
LB6_bit | none | BANKMASK(LATB), 6 |
LB7_bit | none | BANKMASK(LATB), 7 |
LC0_bit | none | BANKMASK(LATC), 0 |
LC1_bit | none | BANKMASK(LATC), 1 |
LC2_bit | none | BANKMASK(LATC), 2 |
LC3_bit | none | BANKMASK(LATC), 3 |
LC4_bit | none | BANKMASK(LATC), 4 |
LC5_bit | none | BANKMASK(LATC), 5 |
LC6_bit | none | BANKMASK(LATC), 6 |
LC7_bit | none | BANKMASK(LATC), 7 |
LD0_bit | none | BANKMASK(LATD), 0 |
LD1_bit | none | BANKMASK(LATD), 1 |
LD2_bit | none | BANKMASK(LATD), 2 |
LD3_bit | none | BANKMASK(LATD), 3 |
LD4_bit | none | BANKMASK(LATD), 4 |
LD5_bit | none | BANKMASK(LATD), 5 |
LD6_bit | none | BANKMASK(LATD), 6 |
LD7_bit | none | BANKMASK(LATD), 7 |
LE0_bit | none | BANKMASK(LATE), 0 |
LE1_bit | none | BANKMASK(LATE), 1 |
LE2_bit | none | BANKMASK(LATE), 2 |
LE3_bit | none | BANKMASK(LATE), 3 |
LE4_bit | none | BANKMASK(LATE), 4 |
LE5_bit | none | BANKMASK(LATE), 5 |
LE6_bit | none | BANKMASK(LATE), 6 |
LE7_bit | none | BANKMASK(LATE), 7 |
LVDEN_bit | none | BANKMASK(HLVDCON), 4 |
LVDIE_bit | none | BANKMASK(PIE2), 2 |
LVDIF_bit | none | BANKMASK(PIR2), 2 |
LVDIN_bit | none | BANKMASK(PORTA), 5 |
LVDIP_bit | none | BANKMASK(IPR2), 2 |
LVDL0_bit | none | BANKMASK(HLVDCON), 0 |
LVDL1_bit | none | BANKMASK(HLVDCON), 1 |
LVDL2_bit | none | BANKMASK(HLVDCON), 2 |
LVDL3_bit | none | BANKMASK(HLVDCON), 3 |
LVV0_bit | none | BANKMASK(HLVDCON), 0 |
LVV1_bit | none | BANKMASK(HLVDCON), 1 |
LVV2_bit | none | BANKMASK(HLVDCON), 2 |
LVV3_bit | none | BANKMASK(HLVDCON), 3 |
NEGATIVE_bit | none | BANKMASK(STATUS), 4 |
NOT_A_bit | none | BANKMASK(SSPSTAT), 5 |
NOT_ADDRESS_bit | none | BANKMASK(SSPSTAT), 5 |
NOT_BOR_bit | none | BANKMASK(RCON), 0 |
NOT_DONE_bit | none | BANKMASK(ADCON0), 1 |
NOT_IPEN_bit | none | BANKMASK(RCON), 7 |
NOT_PD_bit | none | BANKMASK(RCON), 2 |
NOT_POR_bit | none | BANKMASK(RCON), 1 |
NOT_RBPU_bit | none | BANKMASK(INTCON2), 7 |
NOT_RI_bit | none | BANKMASK(RCON), 4 |
NOT_T1SYNC_bit | none | BANKMASK(T1CON), 2 |
NOT_T3SYNC_bit | none | BANKMASK(T3CON), 2 |
NOT_TO_bit | none | BANKMASK(RCON), 3 |
NOT_W_bit | none | BANKMASK(SSPSTAT), 2 |
NOT_WRITE_bit | none | BANKMASK(SSPSTAT), 2 |
OERR_bit | none | BANKMASK(RCSTA), 1 |
OESPP_bit | none | BANKMASK(PORTE), 2 |
OSC2_bit | none | BANKMASK(PORTA), 6 |
OSCFIE_bit | none | BANKMASK(PIE2), 7 |
OSCFIF_bit | none | BANKMASK(PIR2), 7 |
OSCFIP_bit | none | BANKMASK(IPR2), 7 |
OSTS_bit | none | BANKMASK(OSCCON), 3 |
OV_bit | none | BANKMASK(STATUS), 3 |
OVERFLOW_bit | none | BANKMASK(STATUS), 3 |
P1A_bit | none | BANKMASK(PORTC), 2 |
P1M0_bit | none | BANKMASK(CCP1CON), 6 |
P1M1_bit | none | BANKMASK(CCP1CON), 7 |
PA1_bit | none | BANKMASK(PORTC), 2 |
PA2_bit | none | BANKMASK(PORTC), 1 |
PA2E_bit | none | BANKMASK(PORTE), 7 |
PB1E_bit | none | BANKMASK(PORTE), 6 |
PB2_bit | none | BANKMASK(PORTE), 2 |
PB3E_bit | none | BANKMASK(PORTE), 4 |
PC1E_bit | none | BANKMASK(PORTE), 5 |
PC2_bit | none | BANKMASK(PORTE), 1 |
PC3E_bit | none | BANKMASK(PORTE), 3 |
PCFG0_bit | none | BANKMASK(ADCON1), 0 |
PCFG1_bit | none | BANKMASK(ADCON1), 1 |
PCFG2_bit | none | BANKMASK(ADCON1), 2 |
PCFG3_bit | none | BANKMASK(ADCON1), 3 |
PD_bit | none | BANKMASK(RCON), 2 |
PD2_bit | none | BANKMASK(PORTE), 0 |
PDC0_bit | none | BANKMASK(ECCP1DEL), 0 |
PDC1_bit | none | BANKMASK(ECCP1DEL), 1 |
PDC2_bit | none | BANKMASK(ECCP1DEL), 2 |
PDC3_bit | none | BANKMASK(ECCP1DEL), 3 |
PDC4_bit | none | BANKMASK(ECCP1DEL), 4 |
PDC5_bit | none | BANKMASK(ECCP1DEL), 5 |
PDC6_bit | none | BANKMASK(ECCP1DEL), 6 |
PEIE_bit | none | BANKMASK(INTCON), 6 |
PEIE_GIEL_bit | none | BANKMASK(INTCON), 6 |
PEN_bit | none | BANKMASK(SSPCON2), 2 |
PGC_bit | none | BANKMASK(PORTB), 6 |
PGD_bit | none | BANKMASK(PORTB), 7 |
PGM_bit | none | BANKMASK(PORTB), 5 |
PIDEE_bit | none | BANKMASK(UEIE), 0 |
PIDEF_bit | none | BANKMASK(UEIR), 0 |
PKTDIS_bit | none | BANKMASK(UCON), 4 |
POR_bit | none | BANKMASK(RCON), 1 |
PPB0_bit | none | BANKMASK(UCFG), 0 |
PPB1_bit | none | BANKMASK(UCFG), 1 |
PPBI_bit | none | BANKMASK(USTAT), 1 |
PPBRST_bit | none | BANKMASK(UCON), 6 |
PRSEN_bit | none | BANKMASK(ECCP1DEL), 7 |
PSA_bit | none | BANKMASK(T0CON), 3 |
PSPIE_bit | none | BANKMASK(PIE1), 7 |
PSPIF_bit | none | BANKMASK(PIR1), 7 |
PSPIP_bit | none | BANKMASK(IPR1), 7 |
PSSAC0_bit | none | BANKMASK(ECCP1AS), 2 |
PSSAC1_bit | none | BANKMASK(ECCP1AS), 3 |
PSSBD0_bit | none | BANKMASK(ECCP1AS), 0 |
PSSBD1_bit | none | BANKMASK(ECCP1AS), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RA0_bit | none | BANKMASK(PORTA), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RA1_bit | none | BANKMASK(PORTA), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RA2_bit | none | BANKMASK(PORTA), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RA3_bit | none | BANKMASK(PORTA), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RA4_bit | none | BANKMASK(PORTA), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RA5_bit | none | BANKMASK(PORTA), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RA6_bit | none | BANKMASK(PORTA), 6 |
RA7_bit | none | BANKMASK(PORTA), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB0_bit | none | BANKMASK(PORTB), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB1_bit | none | BANKMASK(PORTB), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB2_bit | none | BANKMASK(PORTB), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB3_bit | none | BANKMASK(PORTB), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB4_bit | none | BANKMASK(PORTB), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB5_bit | none | BANKMASK(PORTB), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB6_bit | none | BANKMASK(PORTB), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RB7_bit | none | BANKMASK(PORTB), 7 |
RBIE_bit | none | BANKMASK(INTCON), 3 |
RBIF_bit | none | BANKMASK(INTCON), 0 |
RBIP_bit | none | BANKMASK(INTCON2), 0 |
RBPU_bit | none | BANKMASK(INTCON2), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RC0_bit | none | BANKMASK(PORTC), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RC1_bit | none | BANKMASK(PORTC), 1 |
RC1IE_bit | none | BANKMASK(PIE1), 5 |
RC1IF_bit | none | BANKMASK(PIR1), 5 |
RC1IP_bit | none | BANKMASK(IPR1), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RC2_bit | none | BANKMASK(PORTC), 2 |
RC3_bit | none | BANKMASK(PORTC), 3 |
RC4_bit | none | BANKMASK(PORTC), 4 |
RC5_bit | none | BANKMASK(PORTC), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RC6_bit | none | BANKMASK(PORTC), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RC7_bit | none | BANKMASK(PORTC), 7 |
RC8_9_bit | none | BANKMASK(RCSTA), 6 |
RC9_bit | none | BANKMASK(RCSTA), 6 |
RCD8_bit | none | BANKMASK(RCSTA), 0 |
RCEN_bit | none | BANKMASK(SSPCON2), 3 |
RCIDL_bit | none | BANKMASK(BAUDCON), 6 |
RCIE_bit | none | BANKMASK(PIE1), 5 |
RCIF_bit | none | BANKMASK(PIR1), 5 |
RCIP_bit | none | BANKMASK(IPR1), 5 |
RCMT_bit | none | BANKMASK(BAUDCON), 6 |
RD_bit | none | BANKMASK(EECON1), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD0_bit | none | BANKMASK(PORTD), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD1_bit | none | BANKMASK(PORTD), 1 |
RD163_bit | none | BANKMASK(T3CON), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD2_bit | none | BANKMASK(PORTD), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD3_bit | none | BANKMASK(PORTD), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD4_bit | none | BANKMASK(PORTD), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD5_bit | none | BANKMASK(PORTD), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD6_bit | none | BANKMASK(PORTD), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RD7_bit | none | BANKMASK(PORTD), 7 |
RDE_bit | none | BANKMASK(PORTE), 0 |
RDPU_bit | none | BANKMASK(PORTE), 7 |
RDSPP_bit | none | BANKMASK(SPPEPS), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RE0_bit | none | BANKMASK(PORTE), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RE1_bit | none | BANKMASK(PORTE), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RE2_bit | none | BANKMASK(PORTE), 2 |
RE3_bit | none | BANKMASK(PORTE), 3 |
RE4_bit | none | BANKMASK(PORTE), 4 |
RE5_bit | none | BANKMASK(PORTE), 5 |
RE6_bit | none | BANKMASK(PORTE), 6 |
RE7_bit | none | BANKMASK(PORTE), 7 |
READ_WRITE_bit | none | BANKMASK(SSPSTAT), 2 |
RESUME_bit | none | BANKMASK(UCON), 2 |
RI_bit | none | BANKMASK(RCON), 4 |
RJPU_bit | none | BANKMASK(PORTA), 7 |
RSEN_bit | none | BANKMASK(SSPCON2), 1 |
RW_bit | none | BANKMASK(SSPSTAT), 2 |
RX_bit | none | BANKMASK(PORTC), 7 |
RX9_bit | none | BANKMASK(RCSTA), 6 |
RX9D_bit | none | BANKMASK(RCSTA), 0 |
RXCKP_bit | none | BANKMASK(BAUDCON), 5 |
RXDTP_bit | none | BANKMASK(BAUDCON), 5 |
R_NOT_W_bit | none | BANKMASK(SSPSTAT), 2 |
R_W_bit | none | BANKMASK(SSPSTAT), 2 |
R_nW_bit | none | BANKMASK(SSPSTAT), 2 |
SBOREN_bit | none | BANKMASK(RCON), 6 |
SCKP_bit | none | BANKMASK(BAUDCON), 4 |
SCS0_bit | none | BANKMASK(OSCCON), 0 |
SCS1_bit | none | BANKMASK(OSCCON), 1 |
SE0_bit | none | BANKMASK(UCON), 5 |
SEN_bit | none | BANKMASK(SSPCON2), 0 |
SENDB_bit | none | BANKMASK(TXSTA), 3 |
SENDB1_bit | none | BANKMASK(TXSTA), 3 |
SMP_bit | none | BANKMASK(SSPSTAT), 7 |
SOFIE_bit | none | BANKMASK(UIE), 6 |
SOFIF_bit | none | BANKMASK(UIR), 6 |
SOSCEN_bit | none | BANKMASK(T1CON), 3 |
SOSCEN3_bit | none | BANKMASK(T3CON), 3 |
SPEN_bit | none | BANKMASK(RCSTA), 7 |
SPP0_bit | none | BANKMASK(PORTD), 0 |
SPP1_bit | none | BANKMASK(PORTD), 1 |
SPP2_bit | none | BANKMASK(PORTD), 2 |
SPP3_bit | none | BANKMASK(PORTD), 3 |
SPP4_bit | none | BANKMASK(PORTD), 4 |
SPP5_bit | none | BANKMASK(PORTD), 5 |
SPP6_bit | none | BANKMASK(PORTD), 6 |
SPP7_bit | none | BANKMASK(PORTD), 7 |
SPPBUSY_bit | none | BANKMASK(SPPEPS), 4 |
SPPEN_bit | none | BANKMASK(SPPCON), 0 |
SPPIE_bit | none | BANKMASK(PIE1), 7 |
SPPIF_bit | none | BANKMASK(PIR1), 7 |
SPPIP_bit | none | BANKMASK(IPR1), 7 |
SPPOWN_bit | none | BANKMASK(SPPCON), 1 |
SREN_bit | none | BANKMASK(RCSTA), 5 |
SRENA_bit | none | BANKMASK(RCSTA), 5 |
SS2_bit | none | BANKMASK(PORTD), 7 |
SSPEN_bit | none | BANKMASK(SSPCON1), 5 |
SSPIE_bit | none | BANKMASK(PIE1), 3 |
SSPIF_bit | none | BANKMASK(PIR1), 3 |
SSPIP_bit | none | BANKMASK(IPR1), 3 |
SSPM0_bit | none | BANKMASK(SSPCON1), 0 |
SSPM1_bit | none | BANKMASK(SSPCON1), 1 |
SSPM2_bit | none | BANKMASK(SSPCON1), 2 |
SSPM3_bit | none | BANKMASK(SSPCON1), 3 |
SSPOV_bit | none | BANKMASK(SSPCON1), 6 |
STALLIE_bit | none | BANKMASK(UIE), 5 |
STALLIF_bit | none | BANKMASK(UIR), 5 |
START_bit | none | BANKMASK(SSPSTAT), 3 |
STKFUL_bit | none | BANKMASK(STKPTR), 7 |
STKOVF_bit | none | BANKMASK(STKPTR), 7 |
STKPTR0_bit | none | BANKMASK(STKPTR), 0 |
STKPTR1_bit | none | BANKMASK(STKPTR), 1 |
STKPTR2_bit | none | BANKMASK(STKPTR), 2 |
STKPTR3_bit | none | BANKMASK(STKPTR), 3 |
STKPTR4_bit | none | BANKMASK(STKPTR), 4 |
STKUNF_bit | none | BANKMASK(STKPTR), 6 |
STOP_bit | none | BANKMASK(SSPSTAT), 4 |
SUSPND_bit | none | BANKMASK(UCON), 1 |
SWDTE_bit | none | BANKMASK(WDTCON), 0 |
SWDTEN_bit | none | BANKMASK(WDTCON), 0 |
SYNC_bit | none | BANKMASK(TXSTA), 4 |
SYNC1_bit | none | BANKMASK(TXSTA), 4 |
T08BIT_bit | none | BANKMASK(T0CON), 6 |
T0CKI_bit | none | BANKMASK(PORTA), 4 |
T0CS_bit | none | BANKMASK(T0CON), 5 |
T0IE_bit | none | BANKMASK(INTCON), 5 |
T0IF_bit | none | BANKMASK(INTCON), 2 |
T0IP_bit | none | BANKMASK(INTCON2), 2 |
T0PS0_bit | none | BANKMASK(T0CON), 0 |
T0PS1_bit | none | BANKMASK(T0CON), 1 |
T0PS2_bit | none | BANKMASK(T0CON), 2 |
T0SE_bit | none | BANKMASK(T0CON), 4 |
T13CKI_bit | none | BANKMASK(PORTC), 0 |
T1CKPS0_bit | none | BANKMASK(T1CON), 4 |
T1CKPS1_bit | none | BANKMASK(T1CON), 5 |
T1OSCEN_bit | none | BANKMASK(T1CON), 3 |
T1OSI_bit | none | BANKMASK(PORTC), 1 |
T1OSO_bit | none | BANKMASK(PORTC), 0 |
T1RD16_bit | none | BANKMASK(T1CON), 7 |
T1RUN_bit | none | BANKMASK(T1CON), 6 |
T1SYNC_bit | none | BANKMASK(T1CON), 2 |
T2CKPS0_bit | none | BANKMASK(T2CON), 0 |
T2CKPS1_bit | none | BANKMASK(T2CON), 1 |
T2OUTPS0_bit | none | BANKMASK(T2CON), 3 |
T2OUTPS1_bit | none | BANKMASK(T2CON), 4 |
T2OUTPS2_bit | none | BANKMASK(T2CON), 5 |
T2OUTPS3_bit | none | BANKMASK(T2CON), 6 |
T3CCP1_bit | none | BANKMASK(T3CON), 3 |
T3CCP2_bit | none | BANKMASK(T3CON), 6 |
T3CKPS0_bit | none | BANKMASK(T3CON), 4 |
T3CKPS1_bit | none | BANKMASK(T3CON), 5 |
T3NSYNC_bit | none | BANKMASK(T3CON), 2 |
T3RD16_bit | none | BANKMASK(T3CON), 7 |
T3SYNC_bit | none | BANKMASK(T3CON), 2 |
TMR0IE_bit | none | BANKMASK(INTCON), 5 |
TMR0IF_bit | none | BANKMASK(INTCON), 2 |
TMR0IP_bit | none | BANKMASK(INTCON2), 2 |
TMR0ON_bit | none | BANKMASK(T0CON), 7 |
TMR1CS_bit | none | BANKMASK(T1CON), 1 |
TMR1IE_bit | none | BANKMASK(PIE1), 0 |
TMR1IF_bit | none | BANKMASK(PIR1), 0 |
TMR1IP_bit | none | BANKMASK(IPR1), 0 |
TMR1ON_bit | none | BANKMASK(T1CON), 0 |
TMR2IE_bit | none | BANKMASK(PIE1), 1 |
TMR2IF_bit | none | BANKMASK(PIR1), 1 |
TMR2IP_bit | none | BANKMASK(IPR1), 1 |
TMR2ON_bit | none | BANKMASK(T2CON), 2 |
TMR3CS_bit | none | BANKMASK(T3CON), 1 |
TMR3IE_bit | none | BANKMASK(PIE2), 1 |
TMR3IF_bit | none | BANKMASK(PIR2), 1 |
TMR3IP_bit | none | BANKMASK(IPR2), 1 |
TMR3ON_bit | none | BANKMASK(T3CON), 0 |
TO_bit | none | BANKMASK(RCON), 3 |
TOUTPS0_bit | none | BANKMASK(T2CON), 3 |
TOUTPS1_bit | none | BANKMASK(T2CON), 4 |
TOUTPS2_bit | none | BANKMASK(T2CON), 5 |
TOUTPS3_bit | none | BANKMASK(T2CON), 6 |
TRISA0_bit | none | BANKMASK(TRISA), 0 |
TRISA1_bit | none | BANKMASK(TRISA), 1 |
TRISA2_bit | none | BANKMASK(TRISA), 2 |
TRISA3_bit | none | BANKMASK(TRISA), 3 |
TRISA4_bit | none | BANKMASK(TRISA), 4 |
TRISA5_bit | none | BANKMASK(TRISA), 5 |
TRISA6_bit | none | BANKMASK(TRISA), 6 |
TRISB0_bit | none | BANKMASK(TRISB), 0 |
TRISB1_bit | none | BANKMASK(TRISB), 1 |
TRISB2_bit | none | BANKMASK(TRISB), 2 |
TRISB3_bit | none | BANKMASK(TRISB), 3 |
TRISB4_bit | none | BANKMASK(TRISB), 4 |
TRISB5_bit | none | BANKMASK(TRISB), 5 |
TRISB6_bit | none | BANKMASK(TRISB), 6 |
TRISB7_bit | none | BANKMASK(TRISB), 7 |
TRISC0_bit | none | BANKMASK(TRISC), 0 |
TRISC1_bit | none | BANKMASK(TRISC), 1 |
TRISC2_bit | none | BANKMASK(TRISC), 2 |
TRISC3_bit | none | BANKMASK(TRISC), 3 |
TRISC6_bit | none | BANKMASK(TRISC), 6 |
TRISC7_bit | none | BANKMASK(TRISC), 7 |
TRISD0_bit | none | BANKMASK(TRISD), 0 |
TRISD1_bit | none | BANKMASK(TRISD), 1 |
TRISD2_bit | none | BANKMASK(TRISD), 2 |
TRISD3_bit | none | BANKMASK(TRISD), 3 |
TRISD4_bit | none | BANKMASK(TRISD), 4 |
TRISD5_bit | none | BANKMASK(TRISD), 5 |
TRISD6_bit | none | BANKMASK(TRISD), 6 |
TRISD7_bit | none | BANKMASK(TRISD), 7 |
TRISE0_bit | none | BANKMASK(TRISE), 0 |
TRISE1_bit | none | BANKMASK(TRISE), 1 |
TRISE2_bit | none | BANKMASK(TRISE), 2 |
TRMT_bit | none | BANKMASK(TXSTA), 1 |
TRMT1_bit | none | BANKMASK(TXSTA), 1 |
TRNIE_bit | none | BANKMASK(UIE), 3 |
TRNIF_bit | none | BANKMASK(UIR), 3 |
TUN0_bit | none | BANKMASK(OSCTUNE), 0 |
TUN1_bit | none | BANKMASK(OSCTUNE), 1 |
TUN2_bit | none | BANKMASK(OSCTUNE), 2 |
TUN3_bit | none | BANKMASK(OSCTUNE), 3 |
TUN4_bit | none | BANKMASK(OSCTUNE), 4 |
TX_bit | none | BANKMASK(PORTC), 6 |
TX1IE_bit | none | BANKMASK(PIE1), 4 |
TX1IF_bit | none | BANKMASK(PIR1), 4 |
TX1IP_bit | none | BANKMASK(IPR1), 4 |
TX8_9_bit | none | BANKMASK(TXSTA), 6 |
TX9_bit | none | BANKMASK(TXSTA), 6 |
TX91_bit | none | BANKMASK(TXSTA), 6 |
TX9D_bit | none | BANKMASK(TXSTA), 0 |
TX9D1_bit | none | BANKMASK(TXSTA), 0 |
TXCKP_bit | none | BANKMASK(BAUDCON), 4 |
TXD8_bit | none | BANKMASK(TXSTA), 0 |
TXEN_bit | none | BANKMASK(TXSTA), 5 |
TXEN1_bit | none | BANKMASK(TXSTA), 5 |
TXIE_bit | none | BANKMASK(PIE1), 4 |
TXIF_bit | none | BANKMASK(PIR1), 4 |
TXIP_bit | none | BANKMASK(IPR1), 4 |
UA_bit | none | BANKMASK(SSPSTAT), 1 |
UERRIE_bit | none | BANKMASK(UIE), 1 |
UERRIF_bit | none | BANKMASK(UIR), 1 |
ULPWUIN_bit | none | BANKMASK(PORTA), 0 |
UOEMON_bit | none | BANKMASK(UCFG), 6 |
UPP0_bit | none | BANKMASK(UCFG), 0 |
UPP1_bit | none | BANKMASK(UCFG), 1 |
UPUEN_bit | none | BANKMASK(UCFG), 4 |
URSTIE_bit | none | BANKMASK(UIE), 0 |
URSTIF_bit | none | BANKMASK(UIR), 0 |
USBEN_bit | none | BANKMASK(UCON), 3 |
USBIE_bit | none | BANKMASK(PIE2), 5 |
USBIF_bit | none | BANKMASK(PIR2), 5 |
USBIP_bit | none | BANKMASK(IPR2), 5 |
UTEYE_bit | none | BANKMASK(UCFG), 7 |
UTRDIS_bit | none | BANKMASK(UCFG), 3 |
VCFG0_bit | none | BANKMASK(ADCON1), 4 |
VCFG01_bit | none | BANKMASK(ADCON1), 4 |
VCFG1_bit | none | BANKMASK(ADCON1), 5 |
VCFG11_bit | none | BANKMASK(ADCON1), 5 |
VDIRMAG_bit | none | BANKMASK(HLVDCON), 7 |
VREFM_bit | none | BANKMASK(PORTA), 2 |
VREFP_bit | none | BANKMASK(PORTA), 3 |
W4E_bit | none | BANKMASK(BAUDCON), 1 |
WAIT0_bit | none | BANKMASK(PR2), 4 |
WAIT1_bit | none | BANKMASK(PR2), 5 |
WCOL_bit | none | BANKMASK(SSPCON1), 7 |
WM0_bit | none | BANKMASK(PR2), 0 |
WM1_bit | none | BANKMASK(PR2), 1 |
WR_bit | none | BANKMASK(EECON1), 1 |
WRE_bit | none | BANKMASK(PORTE), 1 |
WREN_bit | none | BANKMASK(EECON1), 2 |
WRERR_bit | none | BANKMASK(EECON1), 3 |
WRSPP_bit | none | BANKMASK(SPPEPS), 6 |
WS0_bit | none | BANKMASK(SPPCFG), 0 |
WS1_bit | none | BANKMASK(SPPCFG), 1 |
WS2_bit | none | BANKMASK(SPPCFG), 2 |
WS3_bit | none | BANKMASK(SPPCFG), 3 |
WUE_bit | none | BANKMASK(BAUDCON), 1 |
ZERO_bit | none | BANKMASK(STATUS), 2 |
nA_bit | none | BANKMASK(SSPSTAT), 5 |
nADDRESS_bit | none | BANKMASK(SSPSTAT), 5 |
nBOR_bit | none | BANKMASK(RCON), 0 |
nDONE_bit | none | BANKMASK(ADCON0), 1 |
nIPEN_bit | none | BANKMASK(RCON), 7 |
nPD_bit | none | BANKMASK(RCON), 2 |
nPOR_bit | none | BANKMASK(RCON), 1 |
nRBPU_bit | none | BANKMASK(INTCON2), 7 |
nRI_bit | none | BANKMASK(RCON), 4 |
nT1SYNC_bit | none | BANKMASK(T1CON), 2 |
nT3SYNC_bit | none | BANKMASK(T3CON), 2 |
nTO_bit | none | BANKMASK(RCON), 3 |
nW_bit | none | BANKMASK(SSPSTAT), 2 |
nWRITE_bit | none | BANKMASK(SSPSTAT), 2 |
_PLIB_H | none | |
__ADC_H | none | |
__PCONFIG_H | none | |
ADC_V5 | none | |
CC_V2 | none | |
PWM_V5 | none | |
PWM_V5 | none | |
EAUSART_V5 | none | |
SPI_V1 | none | |
I2C_V1 | none | |
TMR_V2 | none | |
EEP_V2 | none | |
PTB_V1 | none | |
ANCOM_V3 | none | |
MWIRE_V1 | none | |
FLASH_V1_2 | none | |
_IO_H | none | |
BOR_V1 | none | |
LVD_V1 | none | |
STKOVF | none | STKFUL |
PWM1_IO_V1 | none | |
PWM2_IO_V1 | none | |
CC2_IO_V3 | none | |
I2C_IO_V3 | none | |
SPI_IO_V3 | none | |
MWIRE_IO_V1 | none | |
SW_I2C_IO_V2 | none | |
_P18CXX_H | none | |
ADC_INT_ENABLE | empty | (PIR1bits.ADIF=0,INTCONbits.PEIE=1,PIE1bits.ADIE=1) |
ADC_INT_DISABLE | empty | (PIE1bits.ADIE=0) |
ADC_FOSC_2 | none | 0b10001111 |
ADC_FOSC_4 | none | 0b11001111 |
ADC_FOSC_8 | none | 0b10011111 |
ADC_FOSC_16 | none | 0b11011111 |
ADC_FOSC_32 | none | 0b10101111 |
ADC_FOSC_64 | none | 0b11101111 |
ADC_FOSC_RC | none | 0b11111111 |
ADC_0_TAD | none | 0b11110001 |
ADC_2_TAD | none | 0b11110011 |
ADC_4_TAD | none | 0b11110101 |
ADC_6_TAD | none | 0b11110111 |
ADC_8_TAD | none | 0b11111001 |
ADC_12_TAD | none | 0b11111011 |
ADC_16_TAD | none | 0b11111101 |
ADC_20_TAD | none | 0b11111111 |
ADC_INT_ON | none | 0b11111111 |
ADC_INT_OFF | none | 0b01111111 |
ADC_REF_VDD_VREFMINUS | none | 0b11111110 |
ADC_REF_VREFPLUS_VREFMINUS | none | 0b11111111 |
ADC_REF_VREFPLUS_VSS | none | 0b11111101 |
ADC_REF_VDD_VSS | none | 0b11111100 |
ADC_RIGHT_JUST | none | 0b11111111 |
ADC_LEFT_JUST | none | 0b01111111 |
ADC_0ANA | none | 0b11111111 |
ADC_1ANA | none | 0b11111110 |
ADC_2ANA | none | 0b11111101 |
ADC_3ANA | none | 0b11111100 |
ADC_4ANA | none | 0b11111011 |
ADC_5ANA | none | 0b11111010 |
ADC_6ANA | none | 0b11111001 |
ADC_7ANA | none | 0b11111000 |
ADC_8ANA | none | 0b11110111 |
ADC_9ANA | none | 0b11110110 |
ADC_10ANA | none | 0b11110101 |
ADC_11ANA | none | 0b11110100 |
ADC_12ANA | none | 0b11110011 |
ADC_13ANA | none | 0b11110010 |
ADC_14ANA | none | 0b11110001 |
ADC_15ANA | none | 0b11110000 |
ADC_CH0 | none | 0b10000111 |
ADC_CH1 | none | 0b10001111 |
ADC_CH2 | none | 0b10010111 |
ADC_CH3 | none | 0b10011111 |
ADC_CH4 | none | 0b10100111 |
ADC_CH5 | none | 0b10101111 |
ADC_CH6 | none | 0b10110111 |
ADC_CH7 | none | 0b10111111 |
ADC_CH8 | none | 0b11000111 |
ADC_CH9 | none | 0b11001111 |
ADC_CH10 | none | 0b11010111 |
ADC_CH11 | none | 0b11011111 |
ADC_CH12 | none | 0b11100111 |
ADC_CH13 | none | 0b11101111 |
ADC_CH14 | none | 0b11110111 |
ADC_CH15 | none | 0b11111111 |
ADC_VREFPLUS_VDD | none | ADC_REF_VDD_VREFMINUS |
ADC_VREFPLUS_EXT | none | ADC_REF_VREFPLUS_VREFMINUS |
ADC_VREFMINUS_VSS | none | ADC_REF_VREFPLUS_VSS |
ADC_VREFMINUS_EXT | none | ADC_REF_VREFPLUS_VREFMINUS |
__ANCOMP_H | none | |
COMP_1_2_OP_INV | none | 0b11111111 |
COMP_1_OP_INV | none | 0b11011111 |
COMP_2_OP_INV | none | 0b11101111 |
COMP_OP_INV_NONE | none | 0b11001111 |
COMP_1_2_INDP | none | 0b11111010 |
COMP_1_2_INDP_OP | none | 0b11111011 |
COMP_1_2_COMN_REF | none | 0b11111100 |
COMP_1_2_COMN_REF_OP | none | 0b11111101 |
COMP_1_INDP_OP | none | 0b11111001 |
COMP_INT_REF_SAME_IP | none | 0b11110110 |
COMP_INT_REF_MUX_IP | none | 0b11111110 |
COMP_INT_EN | none | 0b11111111 |
COMP_INT_DIS | none | 0b01111111 |
__CAN2510_H | none | |
__SPI_H | none | |
SMPEND | none | 0b10000000 |
SMPMID | none | 0b00000000 |
MODE_00 | none | 0b00000000 |
MODE_01 | none | 0b00000001 |
MODE_10 | none | 0b00000010 |
MODE_11 | none | 0b00000011 |
SSPENB | none | 0b00100000 |
SPI_FOSC_4 | none | 0b00000000 |
SPI_FOSC_16 | none | 0b00000001 |
SPI_FOSC_64 | none | 0b00000010 |
SPI_FOSC_TMR2 | none | 0b00000011 |
SLV_SSON | none | 0b00000100 |
SLV_SSOFF | none | 0b00000101 |
SPI_WREN | none | 6 |
SPI_WRDI | none | 4 |
SPI_RDSR | none | 5 |
SPI_WRSR | none | 1 |
SPI_READ | none | 3 |
SPI_WRITE | none | 2 |
WIP | none | 0 |
WEL | none | 1 |
BP0 | none | 2 |
BP1 | none | 3 |
EnableIntSPI | none | (PIE1bits.SSPIE = 1) |
DisableIntSPI | none | (PIE1bits.SSPIE = 0) |
SetPriorityIntSPI | 1 | (IPR1bits.SSPIP = <0>) |
SPI_Clear_Intr_Status_Bit | none | (PIR1bits.SSPIF = 0) |
SPI_Intr_Status | none | (PIR1bits.SSPIF) |
SPI_Clear_Recv_OV | none | SSPCONbits.SSPOV = 0 |
CloseSPI | empty | (SSPCON1 &=0xDF) |
DataRdySPI | empty | (SSPSTATbits.BF) |
getcSPI | none | ReadSPI |
putcSPI | none | WriteSPI |
CAN2510_NORESET | none | 0xFFFFFF |
CAN2510_RESET | none | 0xFFFF7F |
CAN2510_RXB0_USEFILT | none | 0xFFFFFF |
CAN2510_RXB0_STDMSG | none | 0xFFFFDF |
CAN2510_RXB0_XTDMSG | none | 0xFFFFBF |
CAN2510_RXB0_NOFILT | none | 0xFFFF9F |
CAN2510_RXB0_ROLL | none | 0xFFFFFF |
CAN2510_RXB0_NOROLL | none | 0xFFFFFB |
CAN2510_RXB1_USEFILT | none | 0xFFFFFF |
CAN2510_RXB1_STDMSG | none | 0xFFFFFE |
CAN2510_RXB1_XTDMSG | none | 0xFFFFFD |
CAN2510_RXB1_NOFILT | none | 0xFFFFFC |
CAN2510_RX0BF_OFF | none | 0xFFFFFF |
CAN2510_RX0BF_INT | none | 0xFFFEF7 |
CAN2510_RX0BF_GPOUTH | none | 0xFFFAFF |
CAN2510_RX0BF_GPOUTL | none | 0xFFFEFF |
CAN2510_RX1BF_OFF | none | 0xFFFFFF |
CAN2510_RX1BF_INT | none | 0xFFFDEF |
CAN2510_RX1BF_GPOUTH | none | 0xFFF5FF |
CAN2510_RX1BF_GPOUTL | none | 0xFFFDFF |
CAN2510_REQ_NORMAL | none | 0xFFFFFF |
CAN2510_REQ_SLEEP | none | 0xDFFFFF |
CAN2510_REQ_LOOPBACK | none | 0xBFFFFF |
CAN2510_REQ_LISTEN | none | 0x9FFFFF |
CAN2510_REQ_CONFIG | none | 0x7FFFFF |
CAN2510_CLKOUT_8 | none | 0xFFFFFF |
CAN2510_CLKOUT_4 | none | 0xFEFFFF |
CAN2510_CLKOUT_2 | none | 0xFDFFFF |
CAN2510_CLKOUT_1 | none | 0xFCFFFF |
CAN2510_CLKOUT_OFF | none | 0xF8FFFF |
CAN2510_TX2_GPIN | none | 0xFFFFFF |
CAN2510_TX2_RTS | none | 0xFFBFFF |
CAN2510_TX1_GPIN | none | 0xFFFFFF |
CAN2510_TX1_RTS | none | 0xFFDFFF |
CAN2510_TX0_GPIN | none | 0xFFFFFF |
CAN2510_TX0_RTS | none | 0xFFEFFF |
CAN2510_SJW_1TQ | none | 0xFFFFFF |
CAN2510_SJW_2TQ | none | 0xFFFFBF |
CAN2510_SJW_3TQ | none | 0xFFFF7F |
CAN2510_SJW_4TQ | none | 0xFFFF3F |
CAN2510_BRG_1x | none | 0xFFFFFF |
CAN2510_BRG_2x | none | 0xFFFFFE |
CAN2510_BRG_3x | none | 0xFFFFFD |
CAN2510_BRG_4x | none | 0xFFFFFC |
CAN2510_BRG_5x | none | 0xFFFFFB |
CAN2510_BRG_6x | none | 0xFFFFFA |
CAN2510_BRG_7x | none | 0xFFFFF9 |
CAN2510_BRG_8x | none | 0xFFFFF8 |
CAN2510_BRG_9x | none | 0xFFFFF7 |
CAN2510_BRG_10x | none | 0xFFFFF6 |
CAN2510_BRG_11x | none | 0xFFFFF5 |
CAN2510_BRG_12x | none | 0xFFFFF4 |
CAN2510_BRG_13x | none | 0xFFFFF3 |
CAN2510_BRG_14x | none | 0xFFFFF2 |
CAN2510_BRG_15x | none | 0xFFFFF1 |
CAN2510_BRG_16x | none | 0xFFFFF0 |
CAN2510_BRG_17x | none | 0xFFFFEF |
CAN2510_BRG_18x | none | 0xFFFFEE |
CAN2510_BRG_19x | none | 0xFFFFED |
CAN2510_BRG_20x | none | 0xFFFFEC |
CAN2510_BRG_21x | none | 0xFFFFEB |
CAN2510_BRG_22x | none | 0xFFFFEA |
CAN2510_BRG_23x | none | 0xFFFFE9 |
CAN2510_BRG_24x | none | 0xFFFFE8 |
CAN2510_BRG_25x | none | 0xFFFFE7 |
CAN2510_BRG_26x | none | 0xFFFFE6 |
CAN2510_BRG_27x | none | 0xFFFFE5 |
CAN2510_BRG_28x | none | 0xFFFFE4 |
CAN2510_BRG_29x | none | 0xFFFFE3 |
CAN2510_BRG_30x | none | 0xFFFFE2 |
CAN2510_BRG_31x | none | 0xFFFFE1 |
CAN2510_BRG_32x | none | 0xFFFFE0 |
CAN2510_BRG_33x | none | 0xFFFFDF |
CAN2510_BRG_34x | none | 0xFFFFDE |
CAN2510_BRG_35x | none | 0xFFFFDD |
CAN2510_BRG_36x | none | 0xFFFFDC |
CAN2510_BRG_37x | none | 0xFFFFDB |
CAN2510_BRG_38x | none | 0xFFFFDA |
CAN2510_BRG_39x | none | 0xFFFFD9 |
CAN2510_BRG_40x | none | 0xFFFFD8 |
CAN2510_BRG_41x | none | 0xFFFFD7 |
CAN2510_BRG_42x | none | 0xFFFFD6 |
CAN2510_BRG_43x | none | 0xFFFFD5 |
CAN2510_BRG_44x | none | 0xFFFFD4 |
CAN2510_BRG_45x | none | 0xFFFFD3 |
CAN2510_BRG_46x | none | 0xFFFFD2 |
CAN2510_BRG_47x | none | 0xFFFFD1 |
CAN2510_BRG_48x | none | 0xFFFFD0 |
CAN2510_BRG_49x | none | 0xFFFFCF |
CAN2510_BRG_50x | none | 0xFFFFCE |
CAN2510_BRG_51x | none | 0xFFFFCD |
CAN2510_BRG_52x | none | 0xFFFFCC |
CAN2510_BRG_53x | none | 0xFFFFCB |
CAN2510_BRG_54x | none | 0xFFFFCA |
CAN2510_BRG_55x | none | 0xFFFFC9 |
CAN2510_BRG_56x | none | 0xFFFFC8 |
CAN2510_BRG_57x | none | 0xFFFFC7 |
CAN2510_BRG_58x | none | 0xFFFFC6 |
CAN2510_BRG_59x | none | 0xFFFFC5 |
CAN2510_BRG_60x | none | 0xFFFFC4 |
CAN2510_BRG_61x | none | 0xFFFFC3 |
CAN2510_BRG_62x | none | 0xFFFFC2 |
CAN2510_BRG_63x | none | 0xFFFFC1 |
CAN2510_BRG_64x | none | 0xFFFFC0 |
CAN2510_PH2SOURCE_PH2 | none | 0xFFFFFF |
CAN2510_PH2SOURCE_PH1 | none | 0xFF7FFF |
CAN2510_SAMPLE_3x | none | 0xFFFFFF |
CAN2510_SAMPLE_1x | none | 0xFFBFFF |
CAN2510_PH1SEG_1TQ | none | 0xFFFFFF |
CAN2510_PH1SEG_2TQ | none | 0xFFF7FF |
CAN2510_PH1SEG_3TQ | none | 0xFFEFFF |
CAN2510_PH1SEG_4TQ | none | 0xFFE7FF |
CAN2510_PH1SEG_5TQ | none | 0xFFDFFF |
CAN2510_PH1SEG_6TQ | none | 0xFFD7FF |
CAN2510_PH1SEG_7TQ | none | 0xFFCFFF |
CAN2510_PH1SEG_8TQ | none | 0xFFC7FF |
CAN2510_PROPSEG_1TQ | none | 0xFFFFFF |
CAN2510_PROPSEG_2TQ | none | 0xFFFEFF |
CAN2510_PROPSEG_3TQ | none | 0xFFFDFF |
CAN2510_PROPSEG_4TQ | none | 0xFFFCFF |
CAN2510_PROPSEG_5TQ | none | 0xFFFBFF |
CAN2510_PROPSEG_6TQ | none | 0xFFFAFF |
CAN2510_PROPSEG_7TQ | none | 0xFFF9FF |
CAN2510_PROPSEG_8TQ | none | 0xFFF8FF |
CAN2510_RX_FILTER | none | 0xFFFFFF |
CAN2510_RX_NOFILTER | none | 0xBFFFFF |
CAN2510_PH2SEG_2TQ | none | 0xFFFFFF |
CAN2510_PH2SEG_3TQ | none | 0xFCFFFF |
CAN2510_PH2SEG_4TQ | none | 0xFDFFFF |
CAN2510_PH2SEG_5TQ | none | 0xFAFFFF |
CAN2510_PH2SEG_6TQ | none | 0xFBFFFF |
CAN2510_PH2SEG_7TQ | none | 0xF8FFFF |
CAN2510_PH2SEG_8TQ | none | 0xF9FFFF |
CAN2510_INT_MSGERR | none | 0x7F |
CAN2510_MSGERR_EN | none | 0x7F |
CAN2510_INT_WAKEUP | none | 0xBF |
CAN2510_WAKEUP_EN | none | 0xBF |
CAN2510_INT_ERROR | none | 0xDF |
CAN2510_ERROR_EN | none | 0xDF |
CAN2510_INT_XMT2 | none | 0xEF |
CAN2510_TXB2_EN | none | 0xEF |
CAN2510_INT_XMT1 | none | 0xF7 |
CAN2510_TXB1_EN | none | 0xF7 |
CAN2510_INT_XMT0 | none | 0xFB |
CAN2510_TXB0_EN | none | 0xFB |
CAN2510_INT_RCV1 | none | 0xFD |
CAN2510_RXB1_EN | none | 0xFD |
CAN2510_INT_RCV0 | none | 0xFE |
CAN2510_RXB0_EN | none | 0xFE |
CAN2510_INT_NONE | none | 0xFF |
CAN2510_NONE_EN | none | 0xFF |
CAN2510_SPI_MODE00 | none | MODE_00 |
CAN2510_SPI_MODE01 | none | MODE_01 |
CAN2510_SPI_SMPEND | none | SMPEND |
CAN2510_SPI_SMPMID | none | SMPMID |
CAN2510_SPI_FOSC4 | none | SPI_FOSC_4 |
CAN2510_SPI_FOSC16 | none | SPI_FOSC_16 |
CAN2510_SPI_FOSC64 | none | SPI_FOSC_64 |
CAN2510_SPI_FOSCTMR2 | none | SPI_FOSC_TMR2 |
CAN2510_MODE_NORMAL | none | 0x00 |
CAN2510_MODE_SLEEP | none | 0x20 |
CAN2510_MODE_LOOPBACK | none | 0x40 |
CAN2510_MODE_LISTEN | none | 0x60 |
CAN2510_MODE_CONFIG | none | 0x80 |
CAN2510_PRI_HIGHEST | none | 0x3 |
CAN2510_PRI_HIGH | none | 0x2 |
CAN2510_PRI_LOW | none | 0x1 |
CAN2510_PRI_LOWEST | none | 0x0 |
CAN2510_NO_DATA | none | 0x00 |
CAN2510_XTDRTR | none | 0x01 |
CAN2510_STDRTR | none | 0x02 |
CAN2510_XTDMSG | none | 0x03 |
CAN2510_STDMSG | none | 0x04 |
CAN2510_BUF_0 | none | 0x00 |
CAN2510_BUF_1 | none | 0x01 |
CAN2510_BUF_2 | none | 0x02 |
CAN2510_RXB0 | none | 0x00 |
CAN2510_RXB1 | none | 0x01 |
CAN2510_RXBX | none | 0x02 |
CAN2510_TXB0 | none | 0x00 |
CAN2510_TXB1 | none | 0x01 |
CAN2510_TXB2 | none | 0x02 |
CAN2510_TXB0_B1 | none | 0x03 |
CAN2510_TXB0_B2 | none | 0x05 |
CAN2510_TXB1_B2 | none | 0x06 |
CAN2510_TXB0_B1_B2 | none | 0x07 |
CAN2510_RXM0 | none | 0x00 |
CAN2510_RXM1 | none | 0x01 |
CAN2510_RXF0 | none | 0x00 |
CAN2510_RXF1 | none | 0x01 |
CAN2510_RXF2 | none | 0x02 |
CAN2510_RXF3 | none | 0x03 |
CAN2510_RXF4 | none | 0x04 |
CAN2510_RXF5 | none | 0x05 |
CAN2510_BUS_OFF | none | 0x05 |
BUS_OFF | none | 0x05 |
CAN2510_ERROR_PASSIVE_TX | none | 0x04 |
ERROR_PASSIVE_TX | none | 0x04 |
CAN2510_ERROR_PASSIVE_RX | none | 0x03 |
ERROR_PASSIVE_RX | none | 0x03 |
CAN2510_ERROR_ACTIVE_WITH_TXWARN | none | 0x02 |
ERROR_ACTIVE_WITH_TXWARN | none | 0x02 |
CAN2510_ERROR_ACTIVE_WITH_RXWARN | none | 0x01 |
ERROR_ACTIVE_WITH_RXWARN | none | 0x01 |
CAN2510_ERROR_ACTIVE | none | 0x00 |
ERROR_ACTIVE | none | 0x00 |
CAN2510_ERROR_INT | none | 0x02 |
CAN2510_WAKEUP_INT | none | 0x04 |
CAN2510_TXB2_INT | none | 0x0A |
CAN2510_TXB1_INT | none | 0x08 |
CAN2510_TXB0_INT | none | 0x06 |
CAN2510_RXB1_INT | none | 0x0E |
CAN2510_RXB0_INT | none | 0x0C |
CAN2510_NO_INTS | none | 0x00 |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
__CAPTURE_H | none | |
CAPTURE_INT_ON | none | 0b11111111 |
CAPTURE_INT_OFF | none | 0b01111111 |
CAP_EVERY_FALL_EDGE | none | 0b10000100 |
CAP_EVERY_RISE_EDGE | none | 0b10000101 |
CAP_EVERY_4_RISE_EDGE | none | 0b10000110 |
CAP_EVERY_16_RISE_EDGE | none | 0b10000111 |
C1_EVERY_FALL_EDGE | none | CAP_EVERY_FALL_EDGE |
C1_EVERY_RISE_EDGE | none | CAP_EVERY_RISE_EDGE |
C1_EVERY_4_RISE_EDGE | none | CAP_EVERY_4_RISE_EDGE |
C1_EVERY_16_RISE_EDGE | none | CAP_EVERY_16_RISE_EDGE |
C2_EVERY_FALL_EDGE | none | CAP_EVERY_FALL_EDGE |
C2_EVERY_RISE_EDGE | none | CAP_EVERY_RISE_EDGE |
C2_EVERY_4_RISE_EDGE | none | CAP_EVERY_4_RISE_EDGE |
C2_EVERY_16_RISE_EDGE | none | CAP_EVERY_16_RISE_EDGE |
C3_EVERY_FALL_EDGE | none | CAP_EVERY_FALL_EDGE |
C3_EVERY_RISE_EDGE | none | CAP_EVERY_RISE_EDGE |
C3_EVERY_4_RISE_EDGE | none | CAP_EVERY_4_RISE_EDGE |
C3_EVERY_16_RISE_EDGE | none | CAP_EVERY_16_RISE_EDGE |
C4_EVERY_FALL_EDGE | none | CAP_EVERY_FALL_EDGE |
C4_EVERY_RISE_EDGE | none | CAP_EVERY_RISE_EDGE |
C4_EVERY_4_RISE_EDGE | none | CAP_EVERY_4_RISE_EDGE |
C4_EVERY_16_RISE_EDGE | none | CAP_EVERY_16_RISE_EDGE |
C5_EVERY_FALL_EDGE | none | CAP_EVERY_FALL_EDGE |
C5_EVERY_RISE_EDGE | none | CAP_EVERY_RISE_EDGE |
C5_EVERY_4_RISE_EDGE | none | CAP_EVERY_4_RISE_EDGE |
C5_EVERY_16_RISE_EDGE | none | CAP_EVERY_16_RISE_EDGE |
EC1_EVERY_FALL_EDGE | none | ECAP_EVERY_FALL_EDGE |
EC1_EVERY_RISE_EDGE | none | ECAP_EVERY_RISE_EDGE |
EC1_EVERY_4_RISE_EDGE | none | ECAP_EVERY_4_RISE_EDGE |
EC1_EVERY_16_RISE_EDGE | none | ECAP_EVERY_16_RISE_EDGE |
CP1_TRIS | none | TRISCbits.TRISC2 |
CP2_TRIS | none | TRISEbits.TRISE7 |
CP3_TRIS | none | TRISGbits.TRISG0 |
CP4_TRIS | none | TRISGbits.TRISG3 |
CP5_TRIS | none | TRISGbits.TRISG4 |
CP6_TRIS | none | TRISEbits.TRISE6 |
CP7_TRIS | none | TRISEbits.TRISE5 |
CP8_TRIS | none | TRISEbits.TRISE4 |
CP9_TRIS | none | TRISEbits.TRISE3 |
CP10_TRIS | none | TRISEbits.TRISE2 |
__COMPARE_H | none | |
COM_INT_ON | none | 0b11111111 |
COM_INT_OFF | none | 0b01111111 |
COM_TOGG_MATCH | none | 0b10000010 |
COM_HI_MATCH | none | 0b10001000 |
COM_LO_MATCH | none | 0b10001001 |
COM_UNCHG_MATCH | none | 0b10001010 |
COM_TRIG_SEVNT | none | 0b10001011 |
ECOM_TOGG_MATCH | none | 0b10000010 |
ECOM_HI_MATCH | none | 0b10001000 |
ECOM_LO_MATCH | none | 0b10001001 |
ECOM_UNCHG_MATCH | none | 0b10001010 |
ECOM_TRIG_SEVNT | none | 0b10001011 |
CM1_TRIS | none | TRISCbits.TRISC2 |
CM2_TRIS | none | TRISEbits.TRISE7 |
CM3_TRIS | none | TRISGbits.TRISG0 |
CM4_TRIS | none | TRISGbits.TRISG3 |
CM5_TRIS | none | TRISGbits.TRISG4 |
CM6_TRIS | none | TRISEbits.TRISE6 |
CM7_TRIS | none | TRISEbits.TRISE5 |
CM8_TRIS | none | TRISEbits.TRISE4 |
CM9_TRIS | none | TRISEbits.TRISE3 |
CM10_TRIS | none | TRISEbits.TRISE2 |
__CTMU_H | none | |
__DPSLP_H | none | |
__PPS_H | none | |
iPPSInput | 2 | <0>=<1> |
__mk_in_fn | 1 | IN_FN_<0> |
__mk_in_pin | 1 | IN_PIN_<0> |
PPSInput | 2 | iPPSInput(__mk_in_fn(<0>),__mk_in_pin(<1>)) |
iPPSOutput | 2 | <0>=<1> |
__mk_out_fn | 1 | OUT_FN_<0> |
__mk_out_pin | 1 | OUT_PIN_<0> |
PPSOutput | 2 | iPPSOutput(__mk_out_pin(<0>),__mk_out_fn(<1>)) |
PPSUnLock | empty | {EECON2 = 0b01010101; EECON2 = 0b10101010; PPSCONbits.IOLOCK = 0;} |
PPSLock | empty | {EECON2 = 0b01010101; EECON2 = 0b10101010; PPSCONbits.IOLOCK = 1;} |
__EEP_H | none | |
__FLASH_H | none | |
__GENERIC_TYPE_DEFS_H_ | none | |
__EXTENSION | none | |
__PACKED | none | |
_STDDEF | none | |
offsetof | 2 | ((int)&(((<0> *)0)-><1>)) |
NULL | none | (0) |
_BOOL | none | _BOOL |
PUBLIC | none | |
PROTECTED | none | |
PRIVATE | none | static |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__PACKED | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__PACKED | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
__EXTENSION | none | |
FLASH_WRITE_BLOCK | none | 32 |
FLASH_ERASE_BLOCK | none | 64 |
LoadFlashAddr | 1 | TBLPTRU = ((unsigned char)(<0>>>16)), TBLPTRH = (unsigned char)(((unsigned int)<0>)>>8), TBLPTRL = ((unsigned char)<0>) |
TableRead | 1 | asm("\tTBLRD*"); <0>=TABLAT |
__I2C_H | none | |
SSPENB | none | 0b00100000 |
SLAVE_7 | none | 0b00000110 |
SLAVE_10 | none | 0b00000111 |
MASTER | none | 0b00001000 |
MASTER_FIRMW | none | 0b00001011 |
SLAVE_7_STSP_INT | none | 0b00001110 |
SLAVE_10_STSP_INT | none | 0b00001111 |
SLEW_OFF | none | 0b10000000 |
SLEW_ON | none | 0b00000000 |
EnableIntI2C | none | (PIE1bits.SSPIE = 1) |
EnableIntI2C1 | none | EnableIntI2C |
DisableIntI2C | none | (PIE1bits.SSPIE = 0) |
DisableIntI2C1 | none | DisableIntI2C |
SetPriorityIntI2C | 1 | (IPR1bits.SSPIP = <0>) |
SetPriorityIntI2C1 | none | SetPriorityIntI2C |
I2C_Clear_Intr_Status_Bit | none | (PIR1bits.SSPIF = 0) |
I2C1_Clear_Intr_Status_Bit | none | I2C_Clear_Intr_Status_Bit |
I2C_Intr_Status | none | PIR1bits.SSPIF |
I2C1_Intr_Status | none | I2C_Intr_Status |
getcI2C | none | ReadI2C |
putcI2C | none | WriteI2C |
StopI2C | empty | SSPCON2bits.PEN=1;while(SSPCON2bits.PEN) |
StartI2C | empty | SSPCON2bits.SEN=1;while(SSPCON2bits.SEN) |
RestartI2C | empty | SSPCON2bits.RSEN=1;while(SSPCON2bits.RSEN) |
NotAckI2C | empty | SSPCON2bits.ACKDT=1;SSPCON2bits.ACKEN=1;while(SSPCON2bits.ACKEN) |
AckI2C | empty | SSPCON2bits.ACKDT=0;SSPCON2bits.ACKEN=1;while(SSPCON2bits.ACKEN) |
DataRdyI2C | empty | (SSPSTATbits.BF) |
putcI2C | none | WriteI2C |
I2C_SCL | none | TRISBbits.TRISB1 |
I2C_SDA | none | TRISBbits.TRISB0 |
__MWIRE_H | none | |
MWIRE_FOSC_4 | none | 0x10 |
MWIRE_FOSC_16 | none | 0x11 |
MWIRE_FOSC_64 | none | 0x12 |
MWIRE_FOSC_TMR2 | none | 0x13 |
MW1_DO | none | PORTCbits.RC7 |
MW1_DO_TRIS | none | TRISCbits.TRISC7 |
MW1_DI | none | PORTBbits.RB0 |
MW1_DI_TRIS | none | TRISBbits.TRISB0 |
MW1_CLK | none | PORTBbits.RB1 |
MW1_CLK_TRIS | none | TRISBbits.TRISB1 |
MW2_DO | none | PORTDbits.RD4 |
MW2_DO_TRIS | none | TRISDbits.TRISD4 |
MW2_DI | none | PORTDbits.RD5 |
MW2_DI_TRIS | none | TRISDbits.TRISD5 |
MW2_CLK | none | PORTDbits.RD6 |
MW2_CLK_TRIS | none | TRISDbits.TRISD6 |
DataRdyMwire1 | empty | (MW1_DI) |
DataRdyMwire2 | empty | (MW2_DI) |
DataRdyMwire | empty | (MW1_DI) |
CloseMwire | empty | SSPCON1&=0xDF |
getcMwire | none | ReadMwire |
putcMwire | none | WriteMwire |
__PCPWM_H | none | |
DT_CLK_SRC_FOSC_16 | none | 0b11111111 |
DT_CLK_SRC_FOSC_8 | none | 0b10111111 |
DT_CLK_SRC_FOSC_4 | none | 0b01111111 |
DT_CLK_SRC_FOSC_2 | none | 0b00111111 |
PT_POS_1_1 | none | 0b00001111 |
PT_POS_1_2 | none | 0b00011111 |
PT_POS_1_3 | none | 0b00101111 |
PT_POS_1_4 | none | 0b00111111 |
PT_POS_1_5 | none | 0b01001111 |
PT_POS_1_6 | none | 0b01011111 |
PT_POS_1_7 | none | 0b01101111 |
PT_POS_1_8 | none | 0b01111111 |
PT_POS_1_9 | none | 0b10001111 |
PT_POS_1_10 | none | 0b10011111 |
PT_POS_1_11 | none | 0b10101111 |
PT_POS_1_12 | none | 0b10111111 |
PT_POS_1_13 | none | 0b11001111 |
PT_POS_1_14 | none | 0b11011111 |
PT_POS_1_15 | none | 0b11101111 |
PT_POS_1_16 | none | 0b11111111 |
PT_PRS_1_1 | none | 0b11110011 |
PT_PRS_1_4 | none | 0b11110111 |
PT_PRS_1_16 | none | 0b11111011 |
PT_PRS_1_64 | none | 0b11111111 |
PT_MOD_CNT_UPDN_INT | none | 0b11111111 |
PT_MOD_CNT_UPDN | none | 0b11111110 |
PT_MOD_SNGL_SHOT | none | 0b11111101 |
PT_MOD_FREE_RUN | none | 0b11111100 |
PT_ENABLE | none | 0b11111111 |
PT_DISABLE | none | 0b01111111 |
PT_CNT_UP | none | 0b10111111 |
PT_CNT_DWN | none | 0b11111111 |
PWM_IO_ALL_ODD | none | 0b01111111 |
PWM_IO_1AND3 | none | 0b01101111 |
PWM_IO_ALL | none | 0b01011111 |
PWM_IO_0TO5 | none | 0b01001111 |
PWM_IO_0TO3 | none | 0b00111111 |
PWM_IO_0AND1 | none | 0b00101111 |
PWM_IO_1 | none | 0b00011111 |
PWM_DISABLE | none | 0b00001111 |
PWM_0AND1_INDPEN | none | 0b11111111 |
PWM_0AND1_COMPLI | none | 0b11111110 |
PWM_2AND3_INDPEN | none | 0b11111111 |
PWM_2AND3_COMPLI | none | 0b11111101 |
PWM_4AND5_INDPEN | none | 0b11111111 |
PWM_4AND5_COMPLI | none | 0b11111011 |
PW_SEVT_POS_1_1 | none | 0b00001111 |
PW_SEVT_POS_1_2 | none | 0b00011111 |
PW_SEVT_POS_1_3 | none | 0b00101111 |
PW_SEVT_POS_1_4 | none | 0b00111111 |
PW_SEVT_POS_1_5 | none | 0b01001111 |
PW_SEVT_POS_1_6 | none | 0b01011111 |
PW_SEVT_POS_1_7 | none | 0b01101111 |
PW_SEVT_POS_1_8 | none | 0b01111111 |
PW_SEVT_POS_1_9 | none | 0b10001111 |
PW_SEVT_POS_1_10 | none | 0b10011111 |
PW_SEVT_POS_1_11 | none | 0b10101111 |
PW_SEVT_POS_1_12 | none | 0b10111111 |
PW_SEVT_POS_1_13 | none | 0b11001111 |
PW_SEVT_POS_1_14 | none | 0b11011111 |
PW_SEVT_POS_1_15 | none | 0b11101111 |
PW_SEVT_POS_1_16 | none | 0b11111111 |
PW_SEVT_DIR_UP | none | 0b11110111 |
PW_SEVT_DIR_DWN | none | 0b11111111 |
PW_OP_SYNC | none | 0b11111111 |
PW_OP_ASYNC | none | 0b11111110 |
BRK_FLT_EN | none | FLTCONFIGbits.BRFEN = 1; |
BRK_FLT_DIS | none | FLTCONFIGbits.BRFEN = 0; |
FLT_A_CY_CY | none | FLTCONFIGbits.FLTAMOD = 1; |
FLT_A_CATAS | none | FLTCONFIGbits.FLTAMOD = 0; |
FLT_A_EN | none | FLTCONFIGbits.FLTAEN = 1; |
FLT_A_DIS | none | FLTCONFIGbits.FLTAEN = 0; |
PMP_H | none | |
__PORTB_H | none | |
PORTB_CHANGE_INT_ON | none | 0b11111111 |
PORTB_CHANGE_INT_OFF | none | 0b01111111 |
PORTB_PULLUPS_ON | none | 0b11111110 |
PORTB_PULLUPS_OFF | none | 0b11111111 |
RISING_EDGE_INT | none | 0b11111111 |
FALLING_EDGE_INT | none | 0b11111101 |
PORTB_INT_PRIO_HIGH | none | 0b11111111 |
PORTB_INT_PRIO_LOW | none | 0b10111111 |
EnablePullups | empty | INTCON2bits.RBPU=0 |
DisablePullups | empty | INTCON2bits.RBPU=1 |
ClosePORTB | empty | INTCONbits.RBIE=0, DisablePullups() |
CloseRB0INT | empty | INTCONbits.INT0IE=0 |
CloseRB1INT | empty | INTCON3bits.INT1IE=0 |
CloseRB2INT | empty | INTCON3bits.INT2IE=0 |
__PWM_H | none | |
SINGLE_OUT | none | 0b00111111 |
FULL_OUT_FWD | none | 0b01111111 |
HALF_OUT | none | 0b10111111 |
FULL_OUT_REV | none | 0b11111111 |
IS_DUAL_PWM | 1 | ((<0>) == HALF_OUT) |
IS_QUAD_PWM | 1 | ((<0>) == FULL_OUT_FWD || (<0>) == FULL_OUT_REV) |
PWM_MODE_1 | none | 0b11111100 |
PWM_MODE_2 | none | 0b11111101 |
PWM_MODE_3 | none | 0b11111110 |
PWM_MODE_4 | none | 0b11111111 |
PWM1_TRIS | none | TRISCbits.TRISC2 |
PWM2_TRIS | none | TRISEbits.TRISE7 |
PWM3_TRIS | none | TRISGbits.TRISG0 |
PWM4_TRIS | none | TRISGbits.TRISG3 |
PWM5_TRIS | none | TRISGbits.TRISG4 |
PWM6_TRIS | none | TRISEbits.TRISE6 |
PWM7_TRIS | none | TRISEbits.TRISE5 |
PWM8_TRIS | none | TRISEbits.TRISE4 |
PWM9_TRIS | none | TRISEbits.TRISE3 |
PWM10_TRIS | none | TRISEbits.TRISE2 |
__RESET_H | none | |
WDT_ENABLED | none | |
STVR_ENABLED | none | |
BOR_ENABLED | none | |
__RTCC_H | none | |
__SWI2C16_H | none | |
DATA_LOW | none | TRISBbits.TRISB0 = 0; |
DATA_HI | none | TRISBbits.TRISB0 = 1; |
DATA_LAT | none | LATBbits.LATB0 |
DATA_PIN | none | PORTBbits.RB0 |
CLOCK_LOW | none | TRISBbits.TRISB1 = 0; |
CLOCK_HI | none | TRISBbits.TRISB1 = 1; |
SCLK_LAT | none | LATBbits.LATB1 |
SCLK_PIN | none | PORTBbits.RB1 |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
SWPutcI2C | none | SWWriteI2C |
SWGetcI2C | none | SWReadI2C |
SWNotAckI2C | none | SWAckI2C |
__SW_SPI_H | none | |
SW_CS_PIN | none | PORTBbits.RB2 |
TRIS_SW_CS_PIN | none | TRISBbits.TRISB2 |
SW_DIN_PIN | none | PORTBbits.RB3 |
TRIS_SW_DIN_PIN | none | TRISBbits.TRISB3 |
SW_DOUT_PIN | none | PORTBbits.RB7 |
TRIS_SW_DOUT_PIN | none | TRISBbits.TRISB7 |
SW_SCK_PIN | none | PORTBbits.RB6 |
TRIS_SW_SCK_PIN | none | TRISBbits.TRISB6 |
MODE0 | none | |
SWOpenSPI | none | OpenSWSPI |
SWWriteSPI | none | WriteSWSPI |
SWSetCSSPI | none | SetCSSWSPI |
SWClearCSSPI | none | ClearCSSWSPI |
putcSWSPI | none | WriteSWSPI |
SWputcSPI | none | putcSWSPI |
__SW_UART_H | none | |
getcUART | none | ReadUART |
putcUART | none | WriteUART |
__TIMERS_H | none | |
TIMER_INT_OFF | none | 0b01111111 |
TIMER_INT_ON | none | 0b11111111 |
T0_16BIT | none | 0b10111111 |
T0_8BIT | none | 0b11111111 |
T0_SOURCE_INT | none | 0b11011111 |
T0_SOURCE_EXT | none | 0b11111111 |
T0_EDGE_RISE | none | 0b11101111 |
T0_EDGE_FALL | none | 0b11111111 |
T0_PS_1_1 | none | 0b11111111 |
T0_PS_1_2 | none | 0b11110000 |
T0_PS_1_4 | none | 0b11110001 |
T0_PS_1_8 | none | 0b11110010 |
T0_PS_1_16 | none | 0b11110011 |
T0_PS_1_32 | none | 0b11110100 |
T0_PS_1_64 | none | 0b11110101 |
T0_PS_1_128 | none | 0b11110110 |
T0_PS_1_256 | none | 0b11110111 |
T1_8BIT_RW | none | 0b10111111 |
T1_16BIT_RW | none | 0b11111111 |
T1_PS_1_1 | none | 0b11001111 |
T1_PS_1_2 | none | 0b11011111 |
T1_PS_1_4 | none | 0b11101111 |
T1_PS_1_8 | none | 0b11111111 |
T1_OSC1EN_OFF | none | 0b11110111 |
T1_OSC1EN_ON | none | 0b11111111 |
T1_SYNC_EXT_ON | none | 0b11111011 |
T1_SYNC_EXT_OFF | none | 0b11111111 |
T1_SOURCE_INT | none | 0b11111101 |
T1_SOURCE_EXT | none | 0b11111111 |
T2_POST_1_1 | none | 0b10000111 |
T2_POST_1_2 | none | 0b10001111 |
T2_POST_1_3 | none | 0b10010111 |
T2_POST_1_4 | none | 0b10011111 |
T2_POST_1_5 | none | 0b10100111 |
T2_POST_1_6 | none | 0b10101111 |
T2_POST_1_7 | none | 0b10110111 |
T2_POST_1_8 | none | 0b10111111 |
T2_POST_1_9 | none | 0b11000111 |
T2_POST_1_10 | none | 0b11001111 |
T2_POST_1_11 | none | 0b11010111 |
T2_POST_1_12 | none | 0b11011111 |
T2_POST_1_13 | none | 0b11100111 |
T2_POST_1_14 | none | 0b11101111 |
T2_POST_1_15 | none | 0b11110111 |
T2_POST_1_16 | none | 0b11111111 |
T2_PS_1_1 | none | 0b11111100 |
T2_PS_1_4 | none | 0b11111101 |
T2_PS_1_16 | none | 0b11111110 |
WriteTimer2 | 1 | TMR2 = (<0>) |
ReadTimer2 | empty | TMR2 |
T3_8BIT_RW | none | 0b11111110 |
T3_16BIT_RW | none | 0b11111111 |
T3_PS_1_1 | none | 0b11001111 |
T3_PS_1_2 | none | 0b11011111 |
T3_PS_1_4 | none | 0b11101111 |
T3_PS_1_8 | none | 0b11111111 |
T3_SYNC_EXT_ON | none | 0b11111011 |
T3_SYNC_EXT_OFF | none | 0b11111111 |
T3_SOURCE_INT | none | 0b11111101 |
T3_SOURCE_EXT | none | 0b11111111 |
T3_OSC1EN_ON | empty | T1CONbits.T1OSCEN=1 |
T3_OSC1EN_OFF | empty | T1CONbits.T1OSCEN=0 |
T3_SOURCE_CCP | none | 0b11111111 |
T1_CCP1_T3_CCP2 | none | 0b10111111 |
T1_SOURCE_CCP | none | 0b10110111 |
__USART_H | none | |
MEM_MODEL | none | |
USART_TX_INT_ON | none | 0b11111111 |
USART_TX_INT_OFF | none | 0b01111111 |
USART_RX_INT_ON | none | 0b11111111 |
USART_RX_INT_OFF | none | 0b10111111 |
USART_BRGH_HIGH | none | 0b11111111 |
USART_BRGH_LOW | none | 0b11101111 |
USART_CONT_RX | none | 0b11111111 |
USART_SINGLE_RX | none | 0b11110111 |
USART_SYNC_MASTER | none | 0b11111111 |
USART_SYNC_SLAVE | none | 0b11111011 |
USART_NINE_BIT | none | 0b11111111 |
USART_EIGHT_BIT | none | 0b11111101 |
USART_SYNCH_MODE | none | 0b11111111 |
USART_ASYNCH_MODE | none | 0b11111110 |
USART_ADDEN_ON | none | 0b11111111 |
USART_ADDEN_OFF | none | 0b11011111 |
BAUD_IDLE_CLK_HIGH | none | 0b11111111 |
BAUD_IDLE_CLK_LOW | none | 0b11101111 |
BAUD_16_BIT_RATE | none | 0b11111111 |
BAUD_8_BIT_RATE | none | 0b11110111 |
BAUD_WAKEUP_ON | none | 0b11111111 |
BAUD_WAKEUP_OFF | none | 0b11111101 |
BAUD_AUTO_ON | none | 0b11111111 |
BAUD_AUTO_OFF | none | 0b11111110 |
DataRdyUSART | empty | (PIR1bits.RCIF) |
MEM_MODEL | none | |
getcUSART | none | ReadUSART |
putcUSART | none | WriteUSART |
CloseUSART | empty | RCSTA&=0b01001111,TXSTAbits.TXEN=0,PIE1&=0b11001111 |
BusyUSART | empty | (!TXSTAbits.TRMT) |
BAUD_IDLE_RX_PIN_STATE_HIGH | none | 0b11011111 |
BAUD_IDLE_RX_PIN_STATE_LOW | none | 0b11111111 |
BAUD_IDLE_TX_PIN_STATE_HIGH | none | 0b11101111 |
BAUD_IDLE_TX_PIN_STATE_LOW | none | 0b11111111 |
__XLCD_H | none | |
DATA_PORT | none | PORTB |
TRIS_DATA_PORT | none | TRISB |
RW_PIN | none | LATBbits.LATB6 |
TRIS_RW | none | TRISBbits.TRISB6 |
RS_PIN | none | LATBbits.LATB5 |
TRIS_RS | none | TRISBbits.TRISB5 |
E_PIN | none | LATBbits.LATB4 |
TRIS_E | none | TRISBbits.TRISB4 |
DON | none | 0b00001111 |
DOFF | none | 0b00001011 |
CURSOR_ON | none | 0b00001111 |
CURSOR_OFF | none | 0b00001101 |
BLINK_ON | none | 0b00001111 |
BLINK_OFF | none | 0b00001110 |
SHIFT_CUR_LEFT | none | 0b00000100 |
SHIFT_CUR_RIGHT | none | 0b00000101 |
SHIFT_DISP_LEFT | none | 0b00000110 |
SHIFT_DISP_RIGHT | none | 0b00000111 |
FOUR_BIT | none | 0b00101100 |
EIGHT_BIT | none | 0b00111100 |
LINE_5X7 | none | 0b00110000 |
LINE_5X10 | none | 0b00110100 |
LINES_5X7 | none | 0b00111000 |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
PARAM_SCLASS | none | |
putcXLCD | none | WriteDataXLCD |
PARAM_SCLASS | none | |
__DELAYS_H | none | |
Delay1TCY | empty | _delay(1) |
Delay10TCY | empty | _delay(10) |
_FLASH_UNSUPPORTED | none | __attribute__((__unsupported__("The flash_write routine is no longer supported. Please use the peripheral library functions: WriteBytesFlash, WriteBlockFlash or WriteWordFlash"))) |
_FLASH_UNSUPPORTED | none | __attribute__((__unsupported__("The flash_write routine is no longer supported. Please use the peripheral library functions: WriteBytesFlash, WriteBlockFlash or WriteWordFlash"))) |
FLASH_WRITE | 3 | flash_write(<0>,<1>,<2>) |
flash_erase | 1 | EraseFlash(<0>,(<0>)+1) |
FLASH_ERASE | 1 | EraseFlash(<0>,(<0>)+1) |
_ERRATA_H_ | none | |
ERRATA_4000 | none | (1<<0) |
ERRATA_FASTINTS | none | (1<<1) |
ERRATA_LFSR | none | (1<<2) |
ERRATA_MINUS40 | none | (1<<3) |
ERRATA_RESET | none | (1<<4) |
ERRATA_BSR15 | none | (1<<5) |
ERRATA_DAW | none | (1<<6) |
ERRATA_EEDATARD | none | (1<<7) |
ERRATA_EEADR | none | (1<<8) |
ERRATA_EE_LVD | none | (1<<9) |
ERRATA_FL_LVD | none | (1<<10) |
ERRATA_TBLWTINT | none | (1<<11) |
ERRATA_FW4000 | none | (1<<12) |
ERRATA_RESETRAM | none | (1<<13) |
ERRATA_FETCH | none | (1<<14) |
LOW_BYTE | 1 | ((unsigned char)((<0>)&0xFF)) |
HIGH_BYTE | 1 | ((unsigned char)(((<0>)>>8)&0xFF)) |
LOW_WORD | 1 | ((unsigned short)((<0>)&0xFFFF)) |
HIGH_WORD | 1 | ((unsigned short)(((<0>)>>16)&0xFFFF)) |
CLRWDT | empty | asm(" clrwdt") |
ClrWdt | empty | asm(" clrwdt") |
NOP | empty | asm(" nop") |
Nop | empty | asm(" nop") |
RESET | empty | asm(" reset") |
Reset | empty | asm(" reset") |
SLEEP | empty | asm(" sleep") |
Sleep | empty | asm(" sleep") |
__PROG_CONFIG | 2 | __config(___mkstr(__PROG_CONFIG), ___mkstr(pic18), <0>, <1>) |
__CONFIG | 2 | __config(___mkstr(__CONFIG), ___mkstr(pic18), ___mkstr(<1>)) |
__IDLOC | 1 | __config(___mkstr(__IDLOC), ___mkstr(pic18), ___mkstr(<0>)) |
_EEPROMSIZE | none | 256 |
__EEPROM_DATA | 8 | asm("\tpsect eeprom_data,class=EEDATA"); asm("\tdb\t" ___mkstr(<0>) "," ___mkstr(<1>) "," ___mkstr(<2>) "," ___mkstr(<3>) "," ___mkstr(<4>) "," ___mkstr(<5>) "," ___mkstr(<6>) "," ___mkstr(<7>)) |
_EEPROMSIZE | none | 256 |
_LOAD_EEADR | 1 | (EEADR=((<0>)&0xFF)) |
_EEPROMSIZE | none | 256 |
_CLEAR_EEIF | empty | PIR2bits.EEIF=0 |
_LOAD_TBLPTR | 1 | *((far unsigned char**)&TBLPTR)=(far unsigned char*)(<0>) |
_EEPROMSIZE | none | 256 |
EEPROM_READ | 1 | Read_b_eep(<0>) |
eeprom_read | 1 | Read_b_eep(<0>) |
_EEPROMSIZE | none | 256 |
EEPROM_WRITE | 2 | (Busy_eep(), Write_b_eep(<0>,<1>)) |
eeprom_write | 2 | (Busy_eep(), Write_b_eep(<0>,<1>)) |
T1RD16ON | none | T1CON|=0x80 |
T3RD16ON | none | T3CON|=0x80 |
WRITETIMER0 | 1 | ((void)(TMR0H=((<0>)>>8),TMR0L=((<0>)&0xFF))) |
WRITETIMER1 | 1 | ((void)(TMR1H=((<0>)>>8),TMR1L=((<0>)&0xFF))) |
WRITETIMER3 | 1 | ((void)(TMR3H=((<0>)>>8),TMR3L=((<0>)&0xFF))) |
READTIMER0 | empty | (TMR0) |
READTIMER1 | empty | (TMR1) |
READTIMER3 | empty | (TMR3) |
__delay_us | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000000.0))) |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
__delaywdt_us | 1 | _delaywdt((unsigned long)((<0>)*(_XTAL_FREQ/4000000.0))) |
__delaywdt_ms | 1 | _delaywdt((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
ei | empty | (INTCONbits.GIE = 1) |
di | empty | (INTCONbits.GIE = 0) |
LCD_DEFAULT | none | |
LCD_44780_H | none | |
_STDLIB_ | none | |
RAND_MAX | none | 32767 |
EXIT_SUCCESS | none | 0 |
EXIT_FAILURE | none | 1 |
_DIVTYPES | none | |
strtoul | 3 | ((unsigned long)strtol((<0>),(<1>),(<2>))) |
max | 2 | (((<0>) > (<1>)) ? (<0>) : (<1>)) |
min | 2 | (((<0>) < (<1>)) ? (<0>) : (<1>)) |
DELAY_H | none | |
setQuartz | none | delay_set_quartz |
LCD_D0 | none | LATDbits.LATD4 |
LCD_D1 | none | LATDbits.LATD5 |
LCD_D2 | none | LATDbits.LATD6 |
LCD_D3 | none | LATDbits.LATD7 |
LCD_RS | none | LATDbits.LATD2 |
LCD_E | none | LATDbits.LATD3 |
LCD_RW | none | LATDbits.LATD1 |
LCD_LED | none | LATCbits.LATC1 |
LEFT | none | 0 |
RIGHT | none | 1 |
LCD_LEFT | none | 0 |
LCD_RIGHT | none | 1 |
TURN_ON_LED_LCD | none | 1 |
TURN_OFF_LED_LCD | none | 0 |
LCD_TURN_ON_LED | none | 1 |
LCD_TURN_OFF_LED | none | 0 |
LCD_TURN_ON_LED | none | 1 |
LCD_TURN_OFF_LED | none | 0 |
TURN_ON_CURSOR | none | 1 |
TURN_OFF_CURSOR | none | 0 |
LCD_TURN_ON_CURSOR | none | 1 |
LCD_TURN_OFF_CURSOR | none | 0 |
BLINKING_ON | none | 1 |
BLINKING_OFF | none | 0 |
LCD_BLINKING_ON | none | 1 |
LCD_BLINKING_OFF | none | 0 |
ZERO_CLEANING_ON | none | 0x01 |
ZERO_CLEANING_OFF | none | 0x00 |
LCD_ZERO_CLEANING_ON | none | 0x01 |
LCD_ZERO_CLEANING_OFF | none | 0x00 |
Epulse | none | LCD_enable_pulse |
enable_pulse_LCD | none | LCD_enable_pulse |
SendCommand | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
HomeLCD | none | LCD_home |
home_LCD | none | LCD_home |
ShiftLCD | none | LCD_shift |
shift_LCD | none | LCD_shift |
ShiftCursorLCD | none | LCD_shift_cursor |
shift_cursor_LCD | none | LCD_shift_cursor |
GotoLineLCD | none | LCD_goto_line |
goto_line_LCD | none | LCD_goto_line |
goto_xy_LCD | none | LCD_goto_xy |
WriteCharLCD | none | LCD_write_char |
write_char_LCD | none | LCD_write_char |
WriteStringLCD | none | LCD_write_message |
write_message_LCD | none | LCD_write_message |
WriteVarLCD | none | LCD_write_string |
write_string_LCD | none | LCD_write_string |
WriteIntLCD | none | LCD_write_integer |
write_integer_LCD | none | LCD_write_integer |
ClearLCD | none | LCD_clear |
clear_LCD | none | LCD_clear |
CursorLCD | none | LCD_cursor |
cursor_LCD | none | LCD_cursor |
BacklightLCD | none | LCD_backlight |
backlight_LCD | none | LCD_backlight |
OpenLCD | none | LCD_initialize |
initialize_LCD | none | LCD_initialize |
LCD_E | none | LATDbits.LATD3 |
LCD_E | none | LATDbits.LATD3 |
LCD_D0 | none | LATDbits.LATD4 |
LCD_D1 | none | LATDbits.LATD5 |
LCD_D2 | none | LATDbits.LATD6 |
LCD_D3 | none | LATDbits.LATD7 |
enable_pulse_LCD | none | LCD_enable_pulse |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
goto_line_LCD | none | LCD_goto_line |
shift_cursor_LCD | none | LCD_shift_cursor |
RIGHT | none | 1 |
LCD_RS | none | LATDbits.LATD2 |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
LCD_RS | none | LATDbits.LATD2 |
write_char_LCD | none | LCD_write_char |
write_char_LCD | none | LCD_write_char |
ZERO_CLEANING_ON | none | 0x01 |
write_string_LCD | none | LCD_write_string |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
LCD_LED | none | LATCbits.LATC1 |
LCD_RS | none | LATDbits.LATD2 |
LCD_E | none | LATDbits.LATD3 |
LCD_RW | none | LATDbits.LATD1 |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
send_command_LCD | none | LCD_send_command |
clear_LCD | none | LCD_clear |
cursor_LCD | none | LCD_cursor |
PCF8563_H | none | |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_DO | none | 0x00 |
RTCC_LU | none | 0x01 |
RTCC_MA | none | 0x02 |
RTCC_ME | none | 0x03 |
RTCC_GI | none | 0x04 |
RTCC_VE | none | 0x05 |
RTCC_SA | none | 0x06 |
RTCC_SU | none | 0x00 |
RTCC_MO | none | 0x01 |
RTCC_TU | none | 0x02 |
RTCC_WE | none | 0x03 |
RTCC_TR | none | 0x04 |
RTCC_FR | none | 0x05 |
RTCC_SA | none | 0x06 |
RTCC_ENABLE_ON | none | 0b00000000 |
RTCC_ENABLE_OFF | none | 0b10000000 |
RTCC_CONTROL_REG_2_ADDR | none | 0x01 |
RTCC_SECONDS_ADDR | none | 0x02 |
RTCC_MINUTES_ADDR | none | 0x03 |
RTCC_HOURS_ADDR | none | 0x04 |
RTCC_DAYS_ADDR | none | 0x05 |
RTCC_DAY_WEEK_ADDR | none | 0x06 |
RTCC_MONTHS_ADDR | none | 0x07 |
RTCC_YEARS_ADDR | none | 0x08 |
RTCC_MINUTS_ALARM_ADDR | none | 0x09 |
RTCC_HOURS_ALARM_ADDR | none | 0x0A |
RTCC_DAYS_ALARM_ADDR | none | 0x0B |
RTCC_DAY_WEEK_ALARM_ADDR | none | 0x0C |
RTCC_MAX_MINUTES | none | 0x60 |
RTCC_MAX_HOURS | none | 0x24 |
RTCC_MAX_YEARS | none | 0xA0 |
RTCC_MAX_MONTHS | none | 0x13 |
RTCC_MAX_DAYS | none | 0x32 |
initialize_PCF8563 | none | PCF8563_initialize |
set_seconds_RTCC | none | RTCC_set_seconds |
get_seconds_RTCC | none | RTCC_get_seconds |
set_minutes_RTCC | none | RTCC_set_minutes |
get_minutes_RTCC | none | RTCC_get_minutes |
set_hours_RTCC | none | RTCC_set_hours |
get_hours_RTCC | none | RTCC_get_hours |
get_time_seconds_RTCC | none | RTCC_get_time_seconds |
get_time_RTCC | none | RTCC_get_time |
set_days_RTCC | none | RTCC_set_days |
get_days_RTCC | none | RTCC_get_days |
set_day_of_the_week_RTCC | none | RTCC_set_day_of_the_week |
get_day_of_the_week_RTCC | none | RTCC_get_day_of_the_week |
set_months_RTCC | none | RTCC_set_months |
get_months_RTCC | none | RTCC_get_months |
set_years_RTCC | none | RTCC_set_years |
get_years_RTCC | none | RTCC_get_years |
get_date_RTCC | none | RTCC_get_date |
set_minutes_alarm_RTCC | none | RTCC_set_minutes_alarm |
set_hours_alarm_RTCC | none | RTCC_set_hours_alarm |
set_days_alarm_RTCC | none | RTCC_set_days_alarm |
set_day_of_the_week_alarm_RTCC | none | RTCC_set_day_of_the_week_alarm |
enable_alarm_interrupt_RTCC | none | RTCC_enable_alarm_interrupt |
disable_alarm_interrupt_RTCC | none | RTCC_disable_alarm_interrupt |
is_alarm_ON_RTCC | none | RTCC_is_alarm_ON |
increment_minutes_RTCC | none | RTCC_increment_minutes |
increment_hours_RTCC | none | RTCC_increment_hours |
increment_years_RTCC | none | RTCC_increment_years |
increment_months_RTCC | none | RTCC_increment_months |
increment_days_RTCC | none | RTCC_increment_days |
MASTER | none | 0b00001000 |
SLEW_ON | none | 0b00000000 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_SECONDS_ADDR | none | 0x02 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_SECONDS_ADDR | none | 0x02 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_MINUTES_ADDR | none | 0x03 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_MINUTES_ADDR | none | 0x03 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_HOURS_ADDR | none | 0x04 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_HOURS_ADDR | none | 0x04 |
get_hours_RTCC | none | RTCC_get_hours |
get_minutes_RTCC | none | RTCC_get_minutes |
get_seconds_RTCC | none | RTCC_get_seconds |
get_hours_RTCC | none | RTCC_get_hours |
get_minutes_RTCC | none | RTCC_get_minutes |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_DAYS_ADDR | none | 0x05 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_DAYS_ADDR | none | 0x05 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_DAY_WEEK_ADDR | none | 0x06 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_DAY_WEEK_ADDR | none | 0x06 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_MONTHS_ADDR | none | 0x07 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_MONTHS_ADDR | none | 0x07 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_YEARS_ADDR | none | 0x08 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_YEARS_ADDR | none | 0x08 |
get_days_RTCC | none | RTCC_get_days |
get_months_RTCC | none | RTCC_get_months |
get_years_RTCC | none | RTCC_get_years |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_MINUTS_ALARM_ADDR | none | 0x09 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_HOURS_ALARM_ADDR | none | 0x0A |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_DAYS_ALARM_ADDR | none | 0x0B |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_DAY_WEEK_ALARM_ADDR | none | 0x0C |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_CONTROL_REG_2_ADDR | none | 0x01 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_CONTROL_REG_2_ADDR | none | 0x01 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_CONTROL_REG_2_ADDR | none | 0x01 |
RTCC_WRITE_ADD | none | 0xA2 |
RTCC_CONTROL_REG_2_ADDR | none | 0x01 |
get_minutes_RTCC | none | RTCC_get_minutes |
RTCC_MAX_MINUTES | none | 0x60 |
set_minutes_RTCC | none | RTCC_set_minutes |
get_hours_RTCC | none | RTCC_get_hours |
RTCC_MAX_HOURS | none | 0x24 |
set_hours_RTCC | none | RTCC_set_hours |
get_years_RTCC | none | RTCC_get_years |
RTCC_MAX_YEARS | none | 0xA0 |
set_years_RTCC | none | RTCC_set_years |
get_months_RTCC | none | RTCC_get_months |
RTCC_MAX_MONTHS | none | 0x13 |
set_months_RTCC | none | RTCC_set_months |
get_days_RTCC | none | RTCC_get_days |
RTCC_MAX_DAYS | none | 0x32 |
set_days_RTCC | none | RTCC_set_days |
I2C_EEPROM_H | none | |
initialize_I2C_EEPROM | none | I2C_EEPROM_initialize |
write_I2C_EEPROM | none | I2C_EEPROM_write |
write_I2C_EEPROM_check | none | I2C_EEPROM_write_check |
read_I2C_EEPROM | none | I2C_EEPROM_read |
MASTER | none | 0b00001000 |
SLEW_ON | none | 0b00000000 |
setQuartz | none | delay_set_quartz |
StartI2C | empty | SSPCON2bits.SEN=1;while(SSPCON2bits.SEN) |
StopI2C | empty | SSPCON2bits.PEN=1;while(SSPCON2bits.PEN) |
write_I2C_EEPROM | none | I2C_EEPROM_write |
read_I2C_EEPROM | none | I2C_EEPROM_read |
StartI2C | empty | SSPCON2bits.SEN=1;while(SSPCON2bits.SEN) |
RestartI2C | empty | SSPCON2bits.RSEN=1;while(SSPCON2bits.RSEN) |
NotAckI2C | empty | SSPCON2bits.ACKDT=1;SSPCON2bits.ACKEN=1;while(SSPCON2bits.ACKEN) |
StopI2C | empty | SSPCON2bits.PEN=1;while(SSPCON2bits.PEN) |
INIT_SYS_H | none | |
BUZZER_TEST_H | none | |
LED_STRING_TEST_H | none | |
LCD_TEST_H | none | |
initialize_LCD | none | LCD_initialize |
write_message_LCD | none | LCD_write_message |
goto_line_LCD | none | LCD_goto_line |
write_message_LCD | none | LCD_write_message |
backlight_LCD | none | LCD_backlight |
TURN_ON_LED_LCD | none | 1 |
clear_LCD | none | LCD_clear |
home_LCD | none | LCD_home |
EEPROM_TEST_H | none | |
MASTER | none | 0b00001000 |
SLEW_ON | none | 0b00000000 |
write_I2C_EEPROM | none | I2C_EEPROM_write |
read_I2C_EEPROM | none | I2C_EEPROM_read |
clear_LCD | none | LCD_clear |
home_LCD | none | LCD_home |
write_message_LCD | none | LCD_write_message |
write_message_LCD | none | LCD_write_message |
BUTTONS_TEST_H | none | |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
ANALOG_TEST_H | none | |
DELTA_POS | none | 100 |
DELTA_NEG | none | -100 |
DELTA_LIGTH_POS | none | 30 |
DELTA_LIGTH_NEG | none | -30 |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
DELTA_POS | none | 100 |
DELTA_NEG | none | -100 |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
DELTA_LIGTH_POS | none | 30 |
DELTA_LIGTH_NEG | none | -30 |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
write_char_LCD | none | LCD_write_char |
write_char_LCD | none | LCD_write_char |
shift_cursor_LCD | none | LCD_shift_cursor |
LEFT | none | 0 |
write_integer_LCD | none | LCD_write_integer |
ZERO_CLEANING_ON | none | 0x01 |
shift_cursor_LCD | none | LCD_shift_cursor |
LEFT | none | 0 |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
RS232_TEST_H | none | |
USART_TX_INT_OFF | none | 0b01111111 |
USART_RX_INT_OFF | none | 0b10111111 |
USART_ASYNCH_MODE | none | 0b11111110 |
USART_EIGHT_BIT | none | 0b11111101 |
USART_CONT_RX | none | 0b11111111 |
USART_BRGH_HIGH | none | 0b11111111 |
clear_LCD | none | LCD_clear |
home_LCD | none | LCD_home |
write_message_LCD | none | LCD_write_message |
write_message_LCD | none | LCD_write_message |
RTC_TEST_H | none | |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
MASTER | none | 0b00001000 |
SLEW_ON | none | 0b00000000 |
get_seconds_RTCC | none | RTCC_get_seconds |
get_seconds_RTCC | none | RTCC_get_seconds |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
clear_LCD | none | LCD_clear |
write_message_LCD | none | LCD_write_message |
write_message_LCD | none | LCD_write_message |
write_message_LCD | none | LCD_write_message |