LTlib LaurTec Library  4.0.3
Open Source C Library for Microchip Microcontrollers based on XC8 Compiler
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PIC18F4550_config.h
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1 /*******************************************************************************
2 
3 Author : Mauro Laurenti
4 Version : 1.3
5 Created on Date : 02/02/2013
6 Last update : 30/07/2016
7 
8 CopyRight 2006-2016 all rights are reserved
9 
10 ********************************************************
11 SOFTWARE LICENSE AGREEMENT
12 ********************************************************
13 
14 The usage of the supplied software imply the acceptance of the following license.
15 
16 The software supplied herewith by Mauro Laurenti (the Author)
17 is intended for use solely and exclusively on Microchip PIC Microcontroller (registered mark).
18 The software is owned by the Author, and is protected under applicable copyright laws.
19 All rights are reserved.
20 Any use in violation of the foregoing restrictions may subject the
21 user to criminal sanctions under applicable laws (Italian or International ones), as well as to
22 civil liability for the breach of the terms and conditions of this license.
23 Commercial use is forbidden without a written acknowledgement with the Author.
24 Personal or educational use is allowed if the application containing the following
25 software doesn't aim to commercial use or monetary earning of any kind.
26 
27 THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
28 WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
29 TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
30 PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
31 IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
32 CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
33 
34 ********************************************************
35 PURPOSES
36 ********************************************************
37 
38 This file contains all the configuration words needed for the PIC18F4550.
39 It can be easily adapted to other PICs according to the available configurations.
40 
41 ****** WARNING ******
42 
43 The configurations must be changed to reflect the application needs!
44 
45 *******************************************************************************/
46 
47 
48 #ifndef PIC18F4550_CONFIG_H
49 #define PIC18F4550_CONFIG_H
50 
51 #ifdef __XC8
52  #include <xc.h>
53 #endif
54 
55 
56 //******************************************************************************
57 // LTlib configurations
58 //******************************************************************************
59 #define IO_LIBRARY_SUPPORTED
60 #define INT_LIBRARY_SUPPORTED
61 #define UART_LIBRARY_SUPPORTED
62 #define SPI_LIBRARY_SUPPORTED
63 #define I2C_LIBRARY_SUPPORTED
64 #define EEPROM_LIBRARY_SUPPORTED
65 #define ADC_LIBRARY_SUPPORTED
66 
67 
68 //******************************************************************************
69 // Module Types
70 //******************************************************************************
71 #define UART_MODULE_TYPE_1
72 #define SPI_MODULE_TYPE_1
73 #define I2C_MODULE_TYPE_3
74 #define ADC_MODULE_TYPE_1
75 
76 
77 //******************************************************************************
78 // Peripheral configurations
79 //******************************************************************************
80 #define NUMBER_OF_IO_PORTS 5
81 
82 #define ADC_WITH_NO_ANSEL_REG
83 
84 #define PULL_UP_RESISTORS_AVAILABLE
85 #define PULL_UP_ENABLE_BIT INTCON2bits.RBPU
86 
87 
88 #define ADC_NUMBER_OF_CHANNELS 13
89 #define ADC_ENABLE_BIT ADCON0bits.ADON
90 #define ADC_START_CONVERSION_BIT ADCON0bits.GO
91 #define ADC_CHANNEL_SELECTION_REGISTER ADCON0
92 #define ADC_BUFFER_HIGH ADRESH
93 #define ADC_BUFFER_LOW ADRESL
94 #define ADC_JUSTIFICATION ADCON2bits.ADFM
95 #define ADC_SETTINGS_0 ADCON0
96 #define ADC_SETTINGS_1 ADCON1
97 #define ADC_SETTINGS_2 ADCON2
98 
99 #define ADC_CH0 0x00000001
100 #define ADC_CH1 0x00000002
101 #define ADC_CH2 0x00000004
102 #define ADC_CH3 0x00000008
103 #define ADC_CH4 0x00000010
104 #define ADC_CH5 0x00000020
105 #define ADC_CH6 0x00000040
106 #define ADC_CH7 0x00000080
107 
108 #define ADC_CH8 0x00000100
109 #define ADC_CH9 0x00000200
110 #define ADC_CH10 0x00000400
111 #define ADC_CH11 0x00000800
112 #define ADC_CH12 0x00001000
113 
114 //******************************************************************************
115 // MCU configurations
116 //******************************************************************************
117 // CONFIG1L
118 #pragma config PLLDIV = 1 // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
119 #pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
120 #pragma config USBDIV = 2 // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)
121 
122 // CONFIG1H
123 #pragma config FOSC = HS // Oscillator Selection bits (HS oscillator (HS))
124 #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
125 #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
126 
127 // CONFIG2L
128 #pragma config PWRT = ON // Power-up Timer Enable bit (PWRT enabled)
129 #pragma config BOR = OFF // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
130 #pragma config BORV = 0 // Brown-out Reset Voltage bits (Maximum setting 4.59V)
131 #pragma config VREGEN = OFF // USB Voltage Regulator Enable bit (USB voltage regulator disabled)
132 
133 // CONFIG2H
134 #pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
135 #pragma config WDTPS = 1 // Watchdog Timer Postscale Select bits (1:1)
136 
137 // CONFIG3H
138 #pragma config CCP2MX = ON // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
139 #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
140 #pragma config LPT1OSC = OFF // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
141 #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
142 
143 // CONFIG4L
144 #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
145 #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
146 #pragma config ICPRT = OFF // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
147 #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
148 
149 // CONFIG5L
150 #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
151 #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
152 #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
153 #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
154 
155 // CONFIG5H
156 #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
157 #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
158 
159 // CONFIG6L
160 #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
161 #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
162 #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
163 #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
164 
165 // CONFIG6H
166 #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
167 #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
168 #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
169 
170 // CONFIG7L
171 #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
172 #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
173 #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
174 #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
175 
176 // CONFIG7H
177 #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
178 
179 #endif