LTlib LaurTec Library  4.0.3
Open Source C Library for Microchip Microcontrollers based on XC8 Compiler
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PIC18F14K50_config.h
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1 /*******************************************************************************
2 
3 Author : Mauro Laurenti
4 Version : 1.2
5 Created on Date : 19/06/2013
6 Last update : 30/07/2016
7 
8 CopyRight 2006-2016 all rights are reserved
9 
10 ********************************************************
11 SOFTWARE LICENSE AGREEMENT
12 ********************************************************
13 
14 The usage of the supplied software imply the acceptance of the following license.
15 
16 The software supplied herewith by Mauro Laurenti (the Author)
17 is intended for use solely and exclusively on Microchip PIC Microcontroller (registered mark).
18 The software is owned by the Author, and is protected under applicable copyright laws.
19 All rights are reserved.
20 Any use in violation of the foregoing restrictions may subject the
21 user to criminal sanctions under applicable laws (Italian or International ones), as well as to
22 civil liability for the breach of the terms and conditions of this license.
23 Commercial use is forbidden without a written acknowledgement with the Author.
24 Personal or educational use is allowed if the application containing the following
25 software doesn't aim to commercial use or monetary earning of any kind.
26 
27 THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
28 WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
29 TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
30 PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
31 IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
32 CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
33 
34 ********************************************************
35 PURPOSES
36 ********************************************************
37 
38 This file contains all the configuration words needed for the PIC18F14K50.
39 It can be easily adapted to other PICs according to the available configurations.
40 
41 ****** WARNING ******
42 
43 The configurations must be changed to reflect the application needs!
44 
45 *****************************************************************************/
46 
47 
48 #ifndef PIC18F14K50_CONFIG_H
49 #define PIC18F14K50_CONFIG_H
50 
51 #ifdef __XC8
52  #include <xc.h>
53 #endif
54 
55 //******************************************************************************
56 // LTlib configurations
57 //******************************************************************************
58 #define IO_LIBRARY_SUPPORTED
59 #define INT_LIBRARY_SUPPORTED
60 #define UART_LIBRARY_SUPPORTED
61 #define SPI_LIBRARY_SUPPORTED
62 #define I2C_LIBRARY_SUPPORTED
63 #define EEPROM_LIBRARY_SUPPORTED
64 #define ADC_LIBRARY_SUPPORTED
65 
66 
67 //******************************************************************************
68 // Module Types
69 //******************************************************************************
70 #define UART_MODULE_TYPE_5
71 #define SPI_MODULE_TYPE_5
72 #define I2C_MODULE_TYPE_5
73 #define ADC_MODULE_TYPE_3
74 
75 
76 //******************************************************************************
77 // Peripheral configurations
78 //******************************************************************************
79 #define NUMBER_OF_IO_PORTS 3
80 
81 #define ADC_WITH_ANSEL_2_REG
82 
83 #define PULL_UP_RESISTORS_AVAILABLE
84 #define PULL_UP_ENABLE_BIT INTCON2bits.RABPU
85 
86 #define ADC_NUMBER_OF_CHANNELS 12
87 #define ADC_ENABLE_BIT ADCON0bits.ADON
88 #define ADC_START_CONVERSION_BIT ADCON0bits.GO
89 #define ADC_CHANNEL_SELECTION_REGISTER ADCON0
90 #define ADC_BUFFER_HIGH ADRESH
91 #define ADC_BUFFER_LOW ADRESL
92 #define ADC_JUSTIFICATION ADCON2bits.ADFM
93 #define ADC_SETTINGS_0 ADCON0
94 #define ADC_SETTINGS_1 ADCON1
95 #define ADC_SETTINGS_2 ADCON2
96 
97 // CH0, CH1 and CH2 are not implemented
98 #define ADC_CH0 0x00000001
99 #define ADC_CH1 0x00000002
100 #define ADC_CH2 0x00000004
101 
102 #define ADC_CH3 0x00000008
103 #define ADC_CH4 0x00000010
104 #define ADC_CH5 0x00000020
105 #define ADC_CH6 0x00000040
106 #define ADC_CH7 0x00000080
107 
108 #define ADC_CH8 0x00000100
109 #define ADC_CH9 0x00000200
110 #define ADC_CH10 0x00000400
111 #define ADC_CH11 0x00000800
112 
113 //******************************************************************************
114 // MCU configuration
115 //******************************************************************************
116 
117 // CONFIG1L
118 #pragma config CPUDIV = NOCLKDIV// CPU System Clock Selection bits (No CPU System Clock divide)
119 #pragma config USBDIV = OFF // USB Clock Selection bit (USB clock comes directly from the OSC1/OSC2 oscillator block; no divide)
120 
121 // CONFIG1H
122 #pragma config FOSC = HS // Oscillator Selection bits (HS oscillator)
123 #pragma config PLLEN = ON // 4 X PLL Enable bit (Oscillator multiplied by 4)
124 #pragma config PCLKEN = ON // Primary Clock Enable bit (Primary clock enabled)
125 #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor disabled)
126 #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
127 
128 // CONFIG2L
129 #pragma config PWRTEN = OFF // Power-up Timer Enable bit (PWRT disabled)
130 #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
131 #pragma config BORV = 19 // Brown-out Reset Voltage bits (VBOR set to 1.9 V nominal)
132 
133 // CONFIG2H
134 #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
135 #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
136 
137 // CONFIG3H
138 #pragma config HFOFST = OFF // HFINTOSC Fast Start-up bit (The system clock is held off until the HFINTOSC is stable.)
139 #pragma config MCLRE = OFF // MCLR Pin Enable bit (RA3 input pin enabled; MCLR disabled)
140 
141 // CONFIG4L
142 #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
143 #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
144 #pragma config BBSIZ = OFF // Boot Block Size Select bit (1kW boot block size)
145 #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
146 
147 // CONFIG5L
148 #pragma config CP0 = OFF // Code Protection bit (Block 0 not code-protected)
149 #pragma config CP1 = OFF // Code Protection bit (Block 1 not code-protected)
150 
151 // CONFIG5H
152 #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block not code-protected)
153 #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
154 
155 // CONFIG6L
156 #pragma config WRT0 = OFF // Table Write Protection bit (Block 0 not write-protected)
157 #pragma config WRT1 = OFF // Table Write Protection bit (Block 1 not write-protected)
158 
159 // CONFIG6H
160 #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers not write-protected)
161 #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block not write-protected)
162 #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
163 
164 // CONFIG7L
165 #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 not protected from table reads executed in other blocks)
166 #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 not protected from table reads executed in other blocks)
167 
168 // CONFIG7H
169 #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block not protected from table reads executed in other blocks)
170 
171 
172 #endif