LTlib LaurTec Library  4.0.0 Beta
Open Source C Library for Microchip Microcontrollers based on XC8 Compiler
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PIC18F46K22_config.h
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1 /*******************************************************************************
2 
3 Author : Mauro Laurenti
4 Version : 1.0
5 Created on Date : 16/01/2016
6 Last update : 30/01/2016
7 
8 CopyRight 2006-2015 all rights are reserved
9 
10 ********************************************************
11 SOFTWARE LICENSE AGREEMENT
12 ********************************************************
13 
14 The usage of the supplied software imply the acceptance of the following license.
15 
16 The software supplied herewith by Mauro Laurenti (the Author)
17 is intended for use solely and exclusively on Microchip PIC Microcontroller (registered mark).
18 The software is owned by the Author, and is protected under applicable copyright laws.
19 All rights are reserved.
20 Any use in violation of the foregoing restrictions may subject the
21 user to criminal sanctions under applicable laws (Italian or International ones), as well as to
22 civil liability for the breach of the terms and conditions of this license.
23 Commercial use is forbidden without a written acknowledgement with the Author.
24 Personal or educational use is allowed if the application containing the following
25 software doesn't aim to commercial use or monetary earning of any kind.
26 
27 THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
28 WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
29 TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
30 PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
31 IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
32 CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
33 
34 ********************************************************
35 PURPOSES
36 ********************************************************
37 
38 This file contains all the configuration words needed for the PIC18F46K22.
39 It can be easily adapted to other PICs according to the available configurations.
40 
41 ****** WARNING ******
42 
43 The configurations must be changed to reflect the application needs!
44 
45 *******************************************************************************/
46 
47 
48 #ifndef PIC18F46K22_CONFIG_H
49 #define PIC18F46K22_CONFIG_H
50 
51 #ifdef __XC8
52  #include <xc.h>
53 #endif
54 
55 
56 //******************************************************************************
57 // LTlib configurations
58 //******************************************************************************
59 
60 #define IO_LIBRARY_SUPPORTED
61 #define INT_LIBRARY_SUPPORTED
62 #define UART_LIBRARY_SUPPORTED
63 #define SPI_LIBRARY_SUPPORTED
64 #define I2C_LIBRARY_SUPPORTED
65 #define EEPROM_LIBRARY_SUPPORTED
66 
67 
68 //******************************************************************************
69 // Peripheral configurations
70 //******************************************************************************
71 #define UART_MODULE_TYPE_2
72 #define SPI_MODULE_TYPE_2
73 #define I2C_MODULE_TYPE_2
74 
75 #define NUMBER_OF_IO_PORTS 5
76 #define ADC_WITH_ANSEL_REG
77 
78 #define PULL_UP_RESISTORS_AVAILABLE
79 #define PULL_UP_ENABLE_BIT INTCON2bits.RBPU
80 #define PULL_UP_SINGLE_BIT_ENABLE
81 #define PULL_UP_ENABLE_REGISTER_B WPUB
82 
83 
84 //******************************************************************************
85 // MCU configurations
86 //******************************************************************************
87 
88 // CONFIG1H
89 #pragma config FOSC = HSHP // Oscillator Selection bits (HS oscillator (high power > 16 MHz))
90 #pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)
91 #pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled)
92 #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
93 #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
94 
95 // CONFIG2L
96 #pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
97 #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
98 #pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
99 
100 // CONFIG2H
101 #pragma config WDTEN = OFF // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
102 #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
103 
104 // CONFIG3H
105 #pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
106 #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
107 #pragma config CCP3MX = PORTE0 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is mulitplexed with RE0)
108 #pragma config HFOFST = OFF // HFINTOSC Fast Start-up (HFINTOSC output and ready status are delayed by the oscillator stable status)
109 #pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0)
110 #pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2)
111 #pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
112 
113 // CONFIG4L
114 #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
115 #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
116 #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
117 
118 // CONFIG5L
119 #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
120 #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
121 #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
122 #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)
123 
124 // CONFIG5H
125 #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
126 #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
127 
128 // CONFIG6L
129 #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
130 #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
131 #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
132 #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)
133 
134 // CONFIG6H
135 #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
136 #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
137 #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
138 
139 // CONFIG7L
140 #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
141 #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
142 #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
143 #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
144 
145 // CONFIG7H
146 #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
147 
148 #endif