LTlib LaurTec Library  4.0.3
Open Source C Library for Microchip Microcontrollers based on XC8 Compiler
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PIC18F46K22_config.h
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1 /*******************************************************************************
2 
3 Author : Mauro Laurenti
4 Version : 1.1
5 Created on Date : 16/01/2016
6 Last update : 30/07/2016
7 
8 CopyRight 2006-2016 all rights are reserved
9 
10 ********************************************************
11 SOFTWARE LICENSE AGREEMENT
12 ********************************************************
13 
14 The usage of the supplied software imply the acceptance of the following license.
15 
16 The software supplied herewith by Mauro Laurenti (the Author)
17 is intended for use solely and exclusively on Microchip PIC Microcontroller (registered mark).
18 The software is owned by the Author, and is protected under applicable copyright laws.
19 All rights are reserved.
20 Any use in violation of the foregoing restrictions may subject the
21 user to criminal sanctions under applicable laws (Italian or International ones), as well as to
22 civil liability for the breach of the terms and conditions of this license.
23 Commercial use is forbidden without a written acknowledgement with the Author.
24 Personal or educational use is allowed if the application containing the following
25 software doesn't aim to commercial use or monetary earning of any kind.
26 
27 THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
28 WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
29 TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
30 PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
31 IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
32 CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
33 
34 ********************************************************
35 PURPOSES
36 ********************************************************
37 
38 This file contains all the configuration words needed for the PIC18F46K22.
39 It can be easily adapted to other PICs according to the available configurations.
40 
41 ****** WARNING ******
42 
43 The configurations must be changed to reflect the application needs!
44 
45 *******************************************************************************/
46 
47 
48 #ifndef PIC18F46K22_CONFIG_H
49 #define PIC18F46K22_CONFIG_H
50 
51 #ifdef __XC8
52  #include <xc.h>
53 #endif
54 
55 
56 //******************************************************************************
57 // LTlib configurations
58 //******************************************************************************
59 
60 #define IO_LIBRARY_SUPPORTED
61 #define INT_LIBRARY_SUPPORTED
62 #define UART_LIBRARY_SUPPORTED
63 #define SPI_LIBRARY_SUPPORTED
64 #define I2C_LIBRARY_SUPPORTED
65 #define EEPROM_LIBRARY_SUPPORTED
66 #define ADC_LIBRARY_SUPPORTED
67 
68 
69 //******************************************************************************
70 // Module Types
71 //******************************************************************************
72 #define UART_MODULE_TYPE_2
73 #define SPI_MODULE_TYPE_2
74 #define I2C_MODULE_TYPE_2
75 #define ADC_MODULE_TYPE_2
76 
77 
78 //******************************************************************************
79 // Peripheral configurations
80 //******************************************************************************
81 #define NUMBER_OF_IO_PORTS 5
82 #define ADC_WITH_ANSEL_REG
83 
84 #define PULL_UP_RESISTORS_AVAILABLE
85 #define PULL_UP_ENABLE_BIT INTCON2bits.RBPU
86 #define PULL_UP_SINGLE_BIT_ENABLE
87 #define PULL_UP_ENABLE_REGISTER_B WPUB
88 
89 #define ADC_NUMBER_OF_CHANNELS 28
90 #define ADC_ENABLE_BIT ADCON0bits.ADON
91 #define ADC_START_CONVERSION_BIT ADCON0bits.GO
92 #define ADC_CHANNEL_SELECTION_REGISTER ADCON0
93 #define ADC_BUFFER_HIGH ADRESH
94 #define ADC_BUFFER_LOW ADRESL
95 #define ADC_JUSTIFICATION ADCON2bits.ADFM
96 #define ADC_SETTINGS_0 ADCON0
97 #define ADC_SETTINGS_1 ADCON1
98 #define ADC_SETTINGS_2 ADCON2
99 
100 #define ADC_CH0 0x00000001
101 #define ADC_CH1 0x00000002
102 #define ADC_CH2 0x00000004
103 #define ADC_CH3 0x00000008
104 #define ADC_CH4 0x00000010
105 #define ADC_CH5 0x00000020
106 #define ADC_CH6 0x00000040
107 #define ADC_CH7 0x00000080
108 
109 #define ADC_CH8 0x00000100
110 #define ADC_CH9 0x00000200
111 #define ADC_CH10 0x00000400
112 #define ADC_CH11 0x00000800
113 #define ADC_CH12 0x00001000
114 #define ADC_CH13 0x00002000
115 #define ADC_CH14 0x00004000
116 #define ADC_CH15 0x00008000
117 
118 #define ADC_CH16 0x00010000
119 #define ADC_CH17 0x00020000
120 #define ADC_CH18 0x00040000
121 #define ADC_CH19 0x00080000
122 #define ADC_CH20 0x00100000
123 #define ADC_CH21 0x00200000
124 #define ADC_CH22 0x00400000
125 #define ADC_CH23 0x00800000
126 
127 #define ADC_CH24 0x01000000
128 #define ADC_CH25 0x02000000
129 #define ADC_CH26 0x04000000
130 #define ADC_CH27 0x08000000
131 
132 
133 
134 //******************************************************************************
135 // MCU configurations
136 //******************************************************************************
137 
138 // CONFIG1H
139 #pragma config FOSC = HSHP // Oscillator Selection bits (HS oscillator (high power > 16 MHz))
140 #pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)
141 #pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled)
142 #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
143 #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
144 
145 // CONFIG2L
146 #pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
147 #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
148 #pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
149 
150 // CONFIG2H
151 #pragma config WDTEN = OFF // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
152 #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
153 
154 // CONFIG3H
155 #pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
156 #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
157 #pragma config CCP3MX = PORTE0 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is mulitplexed with RE0)
158 #pragma config HFOFST = OFF // HFINTOSC Fast Start-up (HFINTOSC output and ready status are delayed by the oscillator stable status)
159 #pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0)
160 #pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2)
161 #pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
162 
163 // CONFIG4L
164 #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
165 #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
166 #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
167 
168 // CONFIG5L
169 #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
170 #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
171 #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
172 #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)
173 
174 // CONFIG5H
175 #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
176 #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
177 
178 // CONFIG6L
179 #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
180 #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
181 #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
182 #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)
183 
184 // CONFIG6H
185 #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
186 #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
187 #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
188 
189 // CONFIG7L
190 #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
191 #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
192 #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
193 #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
194 
195 // CONFIG7H
196 #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
197 
198 #endif