PIC18 LaurTec Library
3.0 Beta
Open Source C Library for PIC18 Microcontrollers based on C18 - XC8 Compilers
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PIC18F4431_config.h
Go to the documentation of this file.
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/*******************************************************************************
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Author : Mauro Laurenti
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Version : 1.0
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Created on Date : 02/02/2013
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Last update : 02/02/2013
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CopyRight 2006-2013 all rights are reserved
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/****************************************************************************
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Author : Mauro Laurenti
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Version : 1.0
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Date : 13/01/2013
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CopyRight 2013 all rights are reserved
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********************************************************
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SOFTWARE LICENSE AGREEMENT
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********************************************************
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The usage of the supplied software imply the acceptance of the following license.
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The software supplied herewith by Mauro Laurenti (the Author) is intended for
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use solely and exclusively on Microchip PIC Microcontroller (registered mark).
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The software is owned by the Author, and is protected under applicable
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copyright laws. All rights are reserved.
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Any use in violation of the foregoing restrictions may subject the
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user to criminal sanctions under applicable laws, as well as to civil liability
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for the breach of the terms and conditions of this license.
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Commercial use is forbidden without a written acknowledgment with the Author.
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Personal or educational use is allowed if the application containing the
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following software doesn't aim to commercial use or monetary earning of any kind.
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THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES,
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WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
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TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE AUTHOR SHALL NOT,
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IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
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CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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********************************************************
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PURPOSES
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********************************************************
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This file contains all the configuration words needed for the PIC18F4431.
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It can be easily adapted to other PICs according to the available configurations.
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****** WARNING ******
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The configurations must be changed to reflect the application needs!
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//*****************************************************************************/
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#ifndef PIC18F4431_H
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#define PIC18F4431_H
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#ifdef __XC8
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#include <xc.h>
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#endif
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//******************************************************************************
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// Register: CONFIG1H @ 0x300001
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//******************************************************************************
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//Internal External Oscillator Switchover bit
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//OFF Internal External Switchover mode disabled
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//ON Internal External Switchover mode enabled
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#pragma config IESO = OFF
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//Oscillator Selection bits
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//RC 11XX External RC oscillator, CLKO function on RA6
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//RC1 101X External RC oscillator, CLKO function on RA6
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//IRCIO Internal oscillator block, port function on RA6 and port function on RA7
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//RCIO External RC oscillator, port function on RA6
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//RC2 External RC oscillator, CLKO function on RA6
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//XT XT oscillator
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//LP LP oscillator
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//IRC Internal oscillator block, CLKO function on RA6 and port function on RA7
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//HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
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//ECIO EC oscillator, port function on RA6
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//EC EC oscillator, CLKO function on RA6
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//HS HS oscillator
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#pragma config OSC = HSPLL
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//Fail-Safe Clock Monitor Enable bit
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//OFF Fail-Safe Clock Monitor disabled
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//ON Fail-Safe Clock Monitor enabled
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#pragma config FCMEN = OFF
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//******************************************************************************
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// Register: CONFIG2L @ 0x300002
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//******************************************************************************
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//Brown-out Reset Enable bits
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//OFF Brown-out Reset disabled
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//ON Brown-out Reset enabled
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#pragma config BOREN = OFF
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//Brown Out Reset Voltage bits
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//42 VBOR set to 4.2V
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//27 VBOR set to 2.7V
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//45 VBOR set to 4.5V
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#pragma config BORV = 42
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//Power-up Timer Enable bit
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//OFF PWRT disabled
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//ON PWRT enabled
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#pragma config PWRTEN = OFF
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//******************************************************************************
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// Register: CONFIG2H @ 0x300003
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//******************************************************************************
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//Watchdog Timer Postscale Select bits
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//8 1:8
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//1 1:1
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//32768 1:32768
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//1024 1:1024
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//2 1:2
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//32 1:32
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//16 1:16
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//16384 1:16384
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//128 1:128
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//4096 1:4096
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//64 1:64
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//8192 1:8192
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//2048 1:2048
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//512 1:512
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//256 1:256
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//4 1:4
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#pragma config WDPS = 1
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//Watchdog Timer Enable bit
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//OFF WDT disabled (control is placed on the SWDTEN bit)
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//ON WDT enabled
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//WINEN = Watchdog Timer Window Enable bit
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//OFF WDT window disabled
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//ON WDT window enabledbled
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#pragma config WDTEN = OFF
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//******************************************************************************
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// Register: CONFIG3L @ 0x300004
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//******************************************************************************
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//Timer1 Oscillator MUX
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//OFF Standard (legacy) Timer1 oscillator operation
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//ON Low-power Timer1 operation when microcontroller is in Sleep mode
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#pragma config T1OSCMX = OFF
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//PWM output pins Reset state control
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//OFF PWM outputs disabled upon Reset (default)
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//ON PWM outputs drive active states upon Reset
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#pragma config PWMPIN = OFF
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//High-Side Transistors Polarity
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//HIGH PWM1, 3, 5 and 7 are active-high
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//LOW PWM1, 3, 5 and 7 are active-low
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#pragma config HPOL = HIGH
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//Low-Side Transistors Polarity
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//HIGH PWM0, 2, 4 and 6 are active-high
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//LOW PWM0, 2, 4 and 6 are active-low
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#pragma config LPOL = HIGH
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//******************************************************************************
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// Register: CONFIG3H @ 0x300005
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//******************************************************************************
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//FLTA MUX bit
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//RC1 FLTA input is multiplexed with RC1
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//RD4 FLTA input is multiplexed with RD4
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#pragma config FLTAMX = RD4
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//MCLR Pin Enable bit
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//OFF Disabled
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//ON Enabled
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#pragma config MCLRE = ON
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//PWM4 MUX bit
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//RB5 PWM4 output is multiplexed with RB5
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//RD5 PWM4 output is multiplexed with RD5
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#pragma config PWM4MX = RB5
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//SSP I/O MUX bit
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//RD1 SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2, respectively. SDO output is multiplexed with RD1.
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//RC7 SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7.
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#pragma config SSPMX = RD1
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//TMR0/T5CKI External clock MUX bit
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//RD0 TMR0/T5CKI external clock input is multiplexed with RD0
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//RC3 TMR0/T5CKI external clock input is multiplexed with RC3
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#pragma config EXCLKMX = RD0
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//******************************************************************************
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// Register: CONFIG4L @ 0x300006
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//******************************************************************************
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//Background Debugger Enable bit
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//OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
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//ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
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#pragma config DEBUG = OFF
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//Stack Full/Underflow Reset Enable bit
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//OFF Stack full/underflow will not cause Reset
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//ON Stack full/underflow will cause Reset
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#pragma config STVREN = ON
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//Low-Voltage ICSP Enable bit
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//OFF Low-voltage ICSP disabled
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//ON Low-voltage ICSP enabled
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#pragma config LVP = OFF
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//******************************************************************************
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// Register: CONFIG5L @ 0x300008
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//******************************************************************************
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//Code Protection bit
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//OFF Block 0 (000200-000FFFh) not code-protected
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//ON Block 0 (000200-000FFFh) code-protected
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#pragma config CP0 = OFF
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//Code Protection bit
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//OFF Block 1 (001000-001FFF) not code-protected
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//ON Block 1 (001000-001FFF) code-protected
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#pragma config CP1 = OFF
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//Code Protection bit
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//OFF Block 2 (002000-002FFFh) not code-protected
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//ON Block 2 (002000-002FFFh) code-protected
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#pragma config CP2 = OFF
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//Code Protection bit
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//OFF Block 3 (003000-003FFFh) not code-protected
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//ON Block 3 (003000-003FFFh) code-protected
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#pragma config CP3 = OFF
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//******************************************************************************
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// Register: CONFIG5H @ 0x300009
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//******************************************************************************
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//Data EEPROM Code Protection bit
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//OFF Data EEPROM not code-protected
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//ON Data EEPROM code-protected
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#pragma config CPD = OFF
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//Boot Block Code Protection bit
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//OFF Boot Block (000000-0001FFh) not code-protected
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//ON Boot Block (000000-0001FFh) code-protected
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#pragma config CPB = OFF
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//******************************************************************************
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// Register: CONFIG6L @ 0x30000A
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//******************************************************************************
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//Write Protection bit
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//OFF Block 0 (000200-000FFFh) not write-protected
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//ON Block 0 (000200-000FFFh) write-protected
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#pragma config WRT0 = OFF
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//Write Protection bit
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//OFF Block 1 (001000-001FFF) not write-protected
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//ON Block 1 (001000-001FFF) write-protected
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#pragma config WRT1 = OFF
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//Write Protection bit
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//OFF Block 2 (002000-002FFFh) not write-protected
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//ON Block 2 (002000-002FFFh) write-protected
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#pragma config WRT2 = OFF
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//Write Protection bit
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//OFF Block 3 (003000-003FFFh) not write-protected
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//ON Block 3 (003000-003FFFh) write-protected
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#pragma config WRT3 = OFF
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//******************************************************************************
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// Register: CONFIG6H @ 0x30000B
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//******************************************************************************
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//Boot Block Write Protection bit
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//OFF Boot Block (000000-0001FFh) not write-protected
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//ON Boot Block (000000-0001FFh) write-protected
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#pragma config WRTB = OFF
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//Configuration Register Write Protection bit
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//OFF Configuration registers (300000-3000FFh) not write-protected
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//ON Configuration registers (300000-3000FFh) write-protected
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#pragma config WRTC = OFF
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//Data EEPROM Write Protection bit
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//OFF Data EEPROM not write-protected
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//ON Data EEPROM write-protected
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#pragma config WRTD = OFF
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//******************************************************************************
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// Register: CONFIG7L @ 0x30000C
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//******************************************************************************
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//Table Read Protection bit
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//OFF Block 0 (000200-000FFFh) not protected from table reads executed in other blocks
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//ON Block 0 (000200-000FFFh) protected from table reads executed in other blocks
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#pragma config EBTR0 = OFF
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//Table Read Protection bit
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//OFF Block 1 (001000-001FFF) not protected from table reads executed in other blocks
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//ON Block 1 (001000-001FFF) protected from table reads executed in other blocks
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#pragma config EBTR1 = OFF
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//Table Read Protection bit
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//OFF Block 2 (002000-002FFFh) not protected from table reads executed in other blocks
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//ON Block 2 (002000-002FFFh) protected from table reads executed in other blocks
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#pragma config EBTR2 = OFF
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//Table Read Protection bit
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//OFF Block 3 (003000-003FFFh) not protected from table reads executed in other blocks
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//ON Block 3 (003000-003FFFh) protected from table reads executed in other blocks
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#pragma config EBTR3 = OFF
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//******************************************************************************
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// Register: CONFIG7H @ 0x30000D
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//******************************************************************************
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//Boot Block Table Read Protection bit
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//OFF Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
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//ON Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
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#pragma config EBTRB = OFF
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#endif
LaurTec_PIC_libraries_v_3.0
conf
PIC18F4431_config.h
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